MCIMX27MOP4AR2 datasheet, PDF - EEWORLD Datasheet

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MCIMX27MOP4AR2: Descriptionprocessors - application specialized bono 19x19 R2; Categorysemiconductor Other integrated circuit (IC); File Size2MB，152 Pages; ManufacturerFREESCALE (NXP); Environmental Compliance

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MCIMX27MOP4AR2 Overview

processors - application specialized bono 19x19 R2

MCIMX27MOP4AR2 Parametric

Parameter Name	Attribute value
Manufacture	Freescale Semiconduc
Product Category	Processors - Application Specialized
RoHS	Yes
Type	Multimedia Applications
Core	ARM926EJ-S
Data Bus Width	32 bi
Operating Supply Voltage	1.38 V to 1.52 V
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	MA-BGA
Memory Type	L1 Cache, ROM, SRAM
Minimum Operating Temperature	- 40 C
Packaging	Reel
Processor Series	i.MX27
Factory Pack Quantity	750
Unit Weigh	1 g

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Freescale Semiconductor

Technical Data

Document Number: MCIMX27EC

Rev. 1.8, 1/2013

i.MX27 and i.MX27L

Data Sheet

Multimedia Applications

Processor

Introduction

Package Information

Plastic Package

Case 1816-01

(MAPBGA–404)

Case 1931-04

(MAPBGA-473)

Ordering Information

See

Table 1 on page 4

for ordering information.

The i.MX27 and i.MX27L (MCIMX27/MX27L)

multimedia applications processors represents the next

step in low-power, high-performance application

processors. Unless otherwise specified, the material in

this data sheet is applicable to both the i.MX27 and

i.MX27L processors and referred to singularly

throughout this document as i.MX27.

The i.MX27L does not include the following features:

ATA-6 HDD Interface, Memory Stick Pro, VPU:

MPEG-4/ H.263/H.264 HW encoder/decoder, and

eMMA (PrP processing, CSC, deblock, dering).

Based on an ARM926EJ-S™ microprocessor core, the

i.MX27/27L processor provides the performance with

low power consumption required by modern digital

devices such as the following:

• Feature-rich cellular phones

• Portable media players and mobile gaming

machines

• Personal digital assistants (PDAs) and wireless

PDAs

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . 4

Functional Description and Application Information . . . . 4

2.1. ARM926 Microprocessor Core Platform . . . . . . . . 4

2.2. Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3. Module Descriptions . . . . . . . . . . . . . . . . . . . . . . . 9

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1. Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . 35

3.2. EMI Pins Multiplexing . . . . . . . . . . . . . . . . . . . . . 35

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 40

4.1. i.MX27/iMX27L Chip-Level Conditions . . . . . . . . 40

4.2. Module-Level Electrical Specifications . . . . . . . . 43

4.3. Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 54

Package Information and Pinout . . . . . . . . . . . . . . . . 109

5.1. Full Package Outline Drawing (17 mm

× 17

mm) 109

5.2. Pin Assignments (17 mm

17 mm) . . . . . . . . . 110

5.3. Full Package Outline Drawing (19 mm

× 19

mm) 129

5.4. Pin Assignments (19 mm

19 mm) . . . . . . . . . 130

Product Documentation . . . . . . . . . . . . . . . . . . . . . . . 150

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Introduction

•

Portable DVD players

Digital cameras

The i.MX27/MX27L processor features the advanced and power-efficient ARM926EJ-S core operating at

speeds up to 400 MHz, and is optimized for minimal power consumption using the most advanced

techniques for power saving (for example, DPTC, power gating, and clock gating). With 90 nm technology

and dual Vt, the i.MX27/MX27L device provides the optimal performance vs. leakage current balance.

The performance of the i.MX27/MX27L processors are both boosted by an on-chip cache system, and

features peripheral devices, such as an MPEG-4, H.263, an H.264 video codec (up to D1—720 x 486—@

30 FPS), LCD, eMMA_lt, and CMOS Sensor Interface controllers.

The i.MX27/MX27L processors supports connections to various types of external memories, such as

266-MHz DDR, NAND Flash, NOR Flash, SDRAM, and SRAM. The i.MX27/MX27L devices can be

connected to a variety of external devices using technology, such as high-speed USBOTG 2.0, the

Advanced Technology Attachment (ATA), Multimedia/Secure Data (MMC/SDIO), and CompactFlash.

NOTE

The i.MX27L does not support the ATA-6 HDD interface.

1.1

Features

The MX27/MX27L processors are targeted for video and voice over-IP (V2IP) and smart remote

controllers. It also provides low-power solutions for any high-performance and demanding multimedia

and graphics applications.

The systems include the following features:

• Multi-standard video codec (i.MX27 only)

— MPEG-4 part-II simple profile encoding/decoding

— H.264/AVC baseline profile encoding/decoding

— H.263 P3 encoding/decoding

— Multi-party call: one stream encoding and two streams decoding simultaneously

— Multi-format: encodes MPEG-4 bitstream, and decodes H.264 bitstream simultaneously

— On-the-fly video processing that reduces system memory load (for example, the

power-efficient viewfinder application with no involvement of either the memory system or the

ARM CPU)

• Advanced power management (i.MX27/27L)

— Dynamic process and temperature compensation

— Multiple clock and power domains

— Independent gating of power domains

• Multiple communication and expansion ports

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

Functional Description and Application Information

1.3

Ordering Information

Table 1. Ordering Information

Device

MCIMX27VOP4A

MCIMX27LVOP4A

MCIMX27MOP4A

MCIMX27LMOP4A

MCIMX27VJP4A

MCIMX27LVJP4A

MCIMX27MJP4A

MCIMX27LMJP4A

Temperature

–20° C to +85° C

–40° C to +85° C

–20° C to +85° C

–40° C to +85° C

Package

1816-01

1931-04

1816-01

1931-04

Table 1

provides ordering information for the MAPBGA, lead-free packages.

2.1

Functional Description and Application Information

ARM926 Microprocessor Core Platform

The ARM926 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 6

3 Multi-Layer AHB

crossbar switch (MAX), and a “primary AHB” complex.

• The instruction bus (I-AHB) of the ARM926EJ-S processor is connected directly to MAX Master

Port 0.

• The data bus (D-AHB) of the ARM926EJ-S processor is connected directly to MAX Master Port 1.

Four alternate bus master interfaces are connected to MAX Master Ports 2–5. Three slave ports of the

MAX are AHB-Lite compliant buses. Slave Port 0 is designated as the “primary” AHB. The primary AHB

is internal to the platform and has five slaves connected to it: the AITC interrupt module, the MCTL

memory controller, and two AIPI peripheral interface gaskets. Slave Ports 1 and 2 of the MAX are referred

to as “secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform.

The ARM926EJ-S processor supports the 32-bit and 16-bit ARM Thumb instruction sets, enabling the

user to trade off between high performance and high-code density. The ARM926EJ-S processor includes

features for efficient execution of Java byte codes, providing Java performance similar to the just-in-time

(JIT) compiler—which is a type of Java compiler—but without the associated code overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both

hardware and software debugging. The ARM926EJ-S processor has a Harvard cached architecture and

provides a complete high-performance processor subsystem, including the following:

• An ARM9EJ-S integer core

• A Memory Management Unit (MMU)

• Separate instruction and data AMBA AHB bus interfaces

• ETM and JTAG-based debug support

i.MX27 and i.MX27L Data Sheet, Rev. 1.8

Freescale Semiconductor

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