5SGXEA7N3F45C3NES datasheet, PDF

Datasheet> All Categories > semiconductor> Other integrated circuit (IC)> 5SGXEA7N3F45C3NES

5SGXEA7N3F45C3NES: Descriptionfpga - field programmable gate array fpga - stratix V GX 2560 labs 840 ios; Categorysemiconductor Other integrated circuit (IC); File Size406KB，21 Pages; ManufacturerAltera (Intel); Environmental Compliance

Download Datasheet Parametric View All

5SGXEA7N3F45C3NES Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	5SGXEA7N3F45C3NES	-	-	View	Buy Now

5SGXEA7N3F45C3NES Overview

fpga - field programmable gate array fpga - stratix V GX 2560 labs 840 ios

5SGXEA7N3F45C3NES Parametric

Parameter Name	Attribute value
Manufacture	Alte
Product Category	FPGA - Field Programmable Gate Array
RoHS	Yes
Produc	Stratix V GX
Number of Logic Elements	622000
Number of Logic Array Blocks - LABs	234720
Total Memory	57.16 Mbi
Number of I/Os	840
Operating Supply Voltage	0.85 V
Maximum Operating Temperature	+ 70 C
Mounting Style	SMD/SMT
Package / Case	FBGA-1932
Data Rate	14.1 Gbps
Embedded Block RAM - EBR	7.16 Mbi
Minimum Operating Temperature	0 C
Number of Transceivers	48
Packaging	Tray

Preview

Download Datasheet

View All

2014.04.08

Stratix V Device Overview

Send Feedback

SV51001

Many of the Stratix

V devices and features are enabled in the Quartus

II software version 13.0. The

remaining devices and features will be enabled in future versions of the Quartus II software.

Altera’s 28-nm Stratix V FPGAs include innovations such as an enhanced core architecture, integrated

transceivers up to 28.05 gigabits per second (Gbps), and a unique array of integrated hard intellectual property

(IP) blocks. With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices

optimized for:

• Bandwidth-centric applications and protocols, including PCI Express

(PCIe

) Gen3

• Data-intensive applications for 40G/100G and beyond

• High-performance, high-precision digital signal processing (DSP) applications

Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a different set of

applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low-risk,

low-cost path to HardCopy

V ASICs.

Related Information

•

Stratix V Device Handbook: Known Issues

Lists the planned updates to the

Stratix V Device Handbook

chapters.

•

Upcoming Stratix V Device Features

Stratix V Family Variants

The Stratix V device family contains the GT, GX, GS, and E variants.

Stratix V GT

devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are optimized for applications that

require ultra-high bandwidth and performance in areas such as 40G/100G/400G optical communications

systems and optical test systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and GX

channels, respectively.

Stratix V GX

devices offer up to 66 integrated transceivers with 14.1-Gbps data rate capability. These

transceivers also support backplane and optical interface applications. These devices are optimized for high-

performance, high-bandwidth applications such as 40G/100G optical transport, packet processing, and

traffic management found in wireline, military communications, and network test equipment markets.

Stratix V GS

devices have an abundance of variable precision DSP blocks, supporting up to 3,926 18x18 or

1,963 27x27 multipliers. In addition, Stratix V GS devices offer integrated transceivers with 14.1-Gbps data

rate capability. These transceivers also support backplane and optical interface applications. These devices

and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other

words and logos identified as trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html.

Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes

no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly

agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Recommended Resources

Two lamps and one switch incandescent lamp parallel lighting circuit

Curler power supply circuit using digital control circuit PT8A320P

A parametric equalizer in imported audio

Band pass source filter circuit using LM110

Simple leakage detector circuit

Standard constant current source circuit composed of CW117

EEWORLD University ---- PCB Design Video - Learn PADS PCB Design in 1 Day: PCB Design Video - Learn PADS PCB Design in 1 Day : https://training.eeworld.com.cn/course/5385This course is suitable for students who are interested in electronics. It is efficient and practical....; pcba68 Embedded System

ccs problem: void delay() in ccs { int i,j; for(i=0;i//int i,j; void delay() { int i,j; for(i=0;i50;i++) for(j=0;j500;j++); } void main() { WDTCTL = WDTPW + WDTHOLD; P1DIR =0x01; while(1) { P1OUT |=0x01; delay(); ...; LengJie Microcontroller MCU

LCD1602 backlight has no effect: [font=微软雅黑][size=5]I need help from you guys. My development board is EP2C8Q208C8. I learned verylog. The store only gave me a vhdl version of the experimental routine, so I used my classmate's progra...; renee FPGA/CPLD

Please ask a question: Try to write out the data structure of the following figure in big-endian and little-endian machines. In the figure below, a and b occupy 4 bits in length. 0 0 1 2 3 4 5 6 7 +-+-+-+-+-+-+-+-+ | | | | ...; mooddog Embedded System

Could you please tell me what this code means?: This code was given to me by my teacher. It was written in the bulkloop framework using keil uvision2 software. void DA5384(unsigned char indata) { unsigned char i; unsigned int mydata; unsigned int d...; hlw0510940108 Embedded System

The weather is too hot to run.: The sun is shining brightly at 8 o'clock. If I keep running like this, I will feel like I'm in Africa. So, starting from tomorrow morning, I will go to Beihang Green Park to jump rope. I have been nea...; soso Talking

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components