EP2S60F1020I4 datasheet, PDF - EEWORLD Datasheet

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EP2S60F1020I4: Descriptionfpga - field programmable gate array fpga - stratix II 3022 labs 718 ios; CategoryProgrammable logic devices Programmable logic; File Size3MB，248 Pages; ManufacturerAltera (Intel)

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fpga - field programmable gate array fpga - stratix II 3022 labs 718 ios

EP2S60F1020I4 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	BGA
package instruction	33 X 33 MM, 1 MM PITCH, FBGA-1020
Contacts	1020
Reach Compliance Code	_compli
ECCN code	3A001.A.7.A
maximum clock frequency	717 MHz
Combined latency of CLB-Max	5.117 ns
JESD-30 code	S-PBGA-B1020
JESD-609 code	e0
length	33 mm
Humidity sensitivity level	3
Configurable number of logic blocks	24176
Number of entries	718
Number of logical units	60440
Output times	710
Number of terminals	1020
Maximum operating temperature	100 °C
Minimum operating temperature	-40 °C
organize	24176 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1020,32X32,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	220
power supply	1.2,1.5/3.3,3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	1.25 V
Minimum supply voltage	1.15 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	33 mm

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Stratix II Device Handbook, Volume 1

101 Innovation Drive

San Jose, CA 95134

www.altera.com

SII5V1-4.5

Contents

Chapter Revision Dates .......................................................................... vii

About this Handbook ................................................................................ i

How to Contact Altera ............................................................................................................................... i

Typographic Conventions ......................................................................................................................... i

Section I. Stratix II Device Family Data Sheet

Revision History ....................................................................................................................... Section I–1

Chapter 1. Introduction

Introduction ............................................................................................................................................ 1–1

Features ................................................................................................................................................... 1–1

Document Revision History ................................................................................................................. 1–6

Chapter 2. Stratix II Architecture

Functional Description .......................................................................................................................... 2–1

Logic Array Blocks ................................................................................................................................ 2–3

LAB Interconnects ............................................................................................................................ 2–4

LAB Control Signals ......................................................................................................................... 2–5

Adaptive Logic Modules ...................................................................................................................... 2–6

ALM Operating Modes ................................................................................................................... 2–9

Register Chain ................................................................................................................................. 2–20

Clear & Preset Logic Control ........................................................................................................ 2–22

MultiTrack Interconnect ..................................................................................................................... 2–22

TriMatrix Memory ............................................................................................................................... 2–28

Memory Block Size ......................................................................................................................... 2–29

Digital Signal Processing Block ......................................................................................................... 2–40

Modes of Operation ....................................................................................................................... 2–44

DSP Block Interface ........................................................................................................................ 2–44

PLLs & Clock Networks ..................................................................................................................... 2–48

Global & Hierarchical Clocking ................................................................................................... 2–48

Enhanced & Fast PLLs ................................................................................................................... 2–57

Enhanced PLLs ............................................................................................................................... 2–68

Fast PLLs .......................................................................................................................................... 2–69

I/O Structure ........................................................................................................................................ 2–69

Double Data Rate I/O Pins ........................................................................................................... 2–77

External RAM Interfacing ............................................................................................................. 2–81

Programmable Drive Strength ..................................................................................................... 2–83

Altera Corporation

iii

Contents

Stratix II Device Handbook, Volume 1

Open-Drain Output ........................................................................................................................ 2–84

Bus Hold .......................................................................................................................................... 2–84

Programmable Pull-Up Resistor .................................................................................................. 2–85

Advanced I/O Standard Support ................................................................................................ 2–85

On-Chip Termination .................................................................................................................... 2–89

MultiVolt I/O Interface ................................................................................................................. 2–93

High-Speed Differential I/O with DPA Support ............................................................................ 2–96

Dedicated Circuitry with DPA Support .................................................................................... 2–100

Fast PLL & Channel Layout ........................................................................................................ 2–102

Document Revision History ............................................................................................................. 2–104

Chapter 3. Configuration & Testing

IEEE Std. 1149.1 JTAG Boundary-Scan Support ............................................................................... 3–1

SignalTap II Embedded Logic Analyzer ............................................................................................ 3–4

Configuration ......................................................................................................................................... 3–4

Operating Modes .............................................................................................................................. 3–5

Configuration Schemes ................................................................................................................... 3–7

Configuring Stratix II FPGAs with JRunner ............................................................................... 3–10

Programming Serial Configuration Devices with SRunner ..................................................... 3–10

Configuring Stratix II FPGAs with the MicroBlaster Driver ................................................... 3–11

PLL Reconfiguration ...................................................................................................................... 3–11

Temperature Sensing Diode (TSD) ................................................................................................... 3–11

Automated Single Event Upset (SEU) Detection ............................................................................ 3–13

Custom-Built Circuitry .................................................................................................................. 3–14

Software Interface ........................................................................................................................... 3–14

Document Revision History ............................................................................................................... 3–14

Chapter 4. Hot Socketing & Power-On Reset

Stratix II

Hot-Socketing Specifications ...............................................................................................................

Devices Can Be Driven Before Power-Up ....................................................................................

I/O Pins Remain Tri-Stated During Power-Up ...........................................................................

Signal Pins Do Not Drive the V

CCIO

, V

CCINT

or V

CCPD

Power Supplies ....................................

Hot Socketing Feature Implementation in Stratix II Devices ..........................................................

Power-On Reset Circuitry ....................................................................................................................

Document Revision History .................................................................................................................

4–1

4–2

4–3

4–5

4–6

Chapter 5. DC & Switching Characteristics

Operating Conditions ........................................................................................................................... 5–1

Absolute Maximum Ratings ........................................................................................................... 5–1

Recommended Operating Conditions .......................................................................................... 5–2

DC Electrical Characteristics .......................................................................................................... 5–3

I/O Standard Specifications ........................................................................................................... 5–4

Bus Hold Specifications ................................................................................................................. 5–17

On-Chip Termination Specifications ........................................................................................... 5–17

Pin Capacitance .............................................................................................................................. 5–19

Power Consumption ........................................................................................................................... 5–20

Altera Corporation

Contents

Timing Model ....................................................................................................................................... 5–20

Preliminary & Final Timing .......................................................................................................... 5–20

I/O Timing Measurement Methodology .................................................................................... 5–21

Performance .................................................................................................................................... 5–27

Internal Timing Parameters .......................................................................................................... 5–34

Stratix II Clock Timing Parameters .............................................................................................. 5–41

Clock Network Skew Adders ....................................................................................................... 5–50

IOE Programmable Delay ............................................................................................................. 5–51

Default Capacitive Loading of Different I/O Standards .......................................................... 5–52

I/O Delays ....................................................................................................................................... 5–54

Maximum Input & Output Clock Toggle Rate .......................................................................... 5–66

Duty Cycle Distortion ......................................................................................................................... 5–77

DCD Measurement Techniques ................................................................................................... 5–78

High-Speed I/O Specifications .......................................................................................................... 5–87

PLL Timing Specifications .................................................................................................................. 5–91

External Memory Interface Specifications ....................................................................................... 5–94

JTAG Timing Specifications ............................................................................................................... 5–96

Document Revision History ............................................................................................................... 5–97

Chapter 6. Reference & Ordering Information

Software ..................................................................................................................................................

Device Pin-Outs .....................................................................................................................................

Ordering Information ...........................................................................................................................

Document Revision History .................................................................................................................

6–1

6–2

Altera Corporation

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