MCF5282 and MCF5216 ColdFire
®
Microcontroller User’s Manual
Devices Supported:
MCF5214
MCF5216
MCF5280
MCF5281
MCF5282
Document Number: MCF5282UM
Rev. 3
2/2009
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MCF5282UM
Rev. 3
2/2009
Overview
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
ColdFire Flash Module (CFM)
Power Management
System Control Module (SCM)
Clock Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Signal Descriptions
Synchronous DRAM Controller Module
DMA Controller Module
Fast Ethernet Controller (FEC)
Watchdog Timer Module
Programmable Interrupt Timer (PIT) Modules
General Purpose Timer (GPT) Modules
DMA Timers
Queued Serial Peripheral Interface Module (QSPI)
UART Modules
I
2
C Module
FlexCAN Module
General Purpose I/O Module
Chip Configuration Module (CCM)
Queued Analog-to-Digital Converter (QADC)
Reset Controller Module
Debug Support
IEEE 1149.1 Test Access Port (JTAG)
Mechanical Data
Electrical Characteristics
Memory Map
Revision History
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
A
B
IND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
A
B
IND
Overview
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
ColdFire Flash Module (CFM)
Power Management
System Control Module (SCM)
Clock Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Signal Descriptions
Synchronous DRAM Controller Module
DMA Controller Module
Fast Ethernet Controller (FEC)
Watchdog Timer Module
Programmable Interrupt Timer (PIT) Modules
General Purpose Timer (GPT) Modules
DMA Timers
Queued Serial Peripheral Interface Module (QSPI)
UART Modules
I
2
C Module
FlexCAN Module
General Purpose I/O Module
Chip Configuration Module (CCM)
Queued Analog-to-Digital Converter (QADC)
Reset Controller Module
Debug Support
IEEE 1149.1 Test Access Port (JTAG)
Mechanical Data
Electrical Characteristics
Memory Map
Revision History
Index
Chapter 1
Overview
1.1
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.1 Version 2 ColdFire Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.1.1.1 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.1.1.2 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.1.1.3 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.1.1.4 Debug Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.1.2 System Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.1.3 External Interface Module (EIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.1.4 Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.1.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.1.6 General Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.1.7 Interrupt Controllers (INTC0/INTC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.1.8 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.1.9 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.1.10 UART Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.1.11 DMA Timers (DTIM0-DTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.1.12 General-Purpose Timers (GPTA/GPTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.1.13 Periodic Interrupt Timers (PIT0-PIT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.1.14 Software Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.1.15 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.1.16 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.1.17 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
MCF5282-Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.1 Fast Ethernet Controller (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.2 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.3 I
2
C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.4 Queued Serial Peripheral Interface (QSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.5 Queued Analog-to-Digital Converter (QADC) . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2
Chapter 2
ColdFire Core
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . .
2.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6 Cache Control Register (CACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7 Access Control Registers (ACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2-1
2-2
2-4
2-4
2-5
2-6
2-7
2-7
2-7
2-7
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor
v
Analogue and Mixed Signal
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