5AGXMB1G4F31I3N datasheet, PDF

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5AGXMB1G4F31I3N: Descriptionfpga - field programmable gate array fpga - arria V GX 11320 labs 384 ios; CategoryProgrammable logic devices Programmable logic; File Size537KB，39 Pages; ManufacturerAltera (Intel); Environmental Compliance

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5AGXMB1G4F31I3N Overview

fpga - field programmable gate array fpga - arria V GX 11320 labs 384 ios

5AGXMB1G4F31I3N Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Altera (Intel)
Parts packaging code	BGA
package instruction	BGA,
Contacts	896
Reach Compliance Code	compliant
ECCN code	3A001.A.7.A
maximum clock frequency	670 MHz
JESD-30 code	S-PBGA-B896
JESD-609 code	e1
length	31 mm
Humidity sensitivity level	3
Configurable number of logic blocks	300000
Number of terminals	896
organize	300000 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Maximum seat height	2.7 mm
Maximum supply voltage	1.18 V
Minimum supply voltage	1.12 V
Nominal supply voltage	1.15 V
surface mount	YES
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	31 mm

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2013.12.26

Arria V Device Overview

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AV-51001

The Arria

V device family consists of the most comprehensive offerings of mid-range FPGAs ranging from

the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest mid-range FPGA

bandwidth 12.5 Gbps transceivers.

The Arria V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging,

switching, and packet processing applications, high-definition video processing and image manipulation,

and intensive digital signal processing (DSP) applications.

Related Information

Arria V Device Handbook: Known Issues

Lists the planned updates to the

Arria V Device Handbook

chapters.

Key Advantages of Arria V Devices

Table 1: Key Advantages of the Arria V Device Family

Advantage

Supporting Feature

Lowest static power in its class

• Built on TSMC's 28 nm process technology and includes an

abundance of hard intellectual property (IP) blocks

• Power-optimized MultiTrack routing and core architecture

• Up to 50% lower power consumption than the previous

generation device

• Lowest power transceivers of any midrange family

• 8-input adaptive logic module (ALM)

• Up to 38.38 megabits (Mb) of embedded memory

• Variable-precision digital signal processing (DSP) blocks

• Serial data rates up to 12.5 Gbps

• Hard memory controllers

Improved logic integration and

differentiation capabilities

Increased bandwidth capacity

Hard processor system (HPS) with

• Tight integration of a dual-core ARM Cortex-A9 MPCore

™

integrated ARM Cortex -A9 MPCore

processor, hard IP, and an FPGA in a single Arria V system-on-

processor

a-chip (SoC)

• Supports over 128 Gbps peak bandwidth with integrated data

coherency between the processor and the FPGA fabric

and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other

words and logos identified as trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html.

Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes

no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly

agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

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