Freescale Semiconductor
HC11
MC68HC11F1
Technical Data
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TABLE OF CONTENTS
Paragraph
Title
SECTION 1INTRODUCTION
1.1
Features .................................................................................................... 1-1
SECTION 2 PIN DESCRIPTIONS
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.11.1
2.11.2
2.11.3
2.11.4
2.11.5
2.11.6
2.11.7
V
DD
and V
SS
.............................................................................................. 2-2
Reset (RESET) .......................................................................................... 2-3
E-Clock Output (E) .................................................................................... 2-3
Crystal Driver and External Clock Input (XTAL, EXTAL) ........................... 2-3
Four Times E-Clock Frequency Output (4XOUT) ..................................... 2-5
Interrupt Request (IRQ) ............................................................................. 2-5
Non-Maskable Interrupt (XIRQ) ................................................................. 2-5
MODA and MODB (MODA/LIR and MODB/V
STBY
) .................................. 2-6
V
RH
and V
RL
.............................................................................................. 2-6
R/W ........................................................................................................... 2-6
Port Signals ............................................................................................... 2-6
Port A ................................................................................................ 2-7
Port B ................................................................................................ 2-8
Port C ................................................................................................ 2-8
Port D ................................................................................................ 2-8
Port E ................................................................................................ 2-9
Port F ................................................................................................. 2-9
Port G ................................................................................................ 2-9
SECTION 3 CENTRAL PROCESSING UNIT
3.1
CPU Registers ........................................................................................... 3-1
3.1.1
Accumulators A, B, and D ................................................................. 3-2
3.1.2
Index Register X (IX) ......................................................................... 3-3
3.1.3
Index Register Y (IY) ......................................................................... 3-3
3.1.4
Stack Pointer (SP) ............................................................................. 3-3
3.1.5
Program Counter (PC) ...................................................................... 3-5
3.1.6
Condition Code Register (CCR) ........................................................ 3-5
3.1.6.1
Carry/Borrow (C) ....................................................................... 3-5
3.1.6.2
Overflow (V) .............................................................................. 3-5
3.1.6.3
Zero (Z) ..................................................................................... 3-6
3.1.6.4
Negative (N) .............................................................................. 3-6
3.1.6.5
Interrupt Mask (I) ....................................................................... 3-6
3.1.6.6
Half Carry (H) ............................................................................ 3-6
3.1.6.7
X Interrupt Mask (X) .................................................................. 3-6
3.1.6.8
Stop Disable (S) ........................................................................ 3-7
Page
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TECHNICAL DATA
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TABLE OF CONTENTS
Paragraph
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.5
(Continued)
Title
Page
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Data Types ................................................................................................ 3-7
Opcodes and Operands ............................................................................ 3-7
Addressing Modes ..................................................................................... 3-7
Immediate .......................................................................................... 3-7
Direct ................................................................................................. 3-8
Extended ........................................................................................... 3-8
Indexed .............................................................................................. 3-8
Inherent ............................................................................................. 3-8
Relative ............................................................................................. 3-8
Instruction Set ........................................................................................... 3-8
SECTION 4OPERATING MODES AND ON-CHIP MEMORY
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.3
4.3
4.3.1
4.3.1.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.2.5
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.1.4
4.4.2
4.4.3
Operating Modes ....................................................................................... 4-1
Single-Chip Operating Mode ............................................................. 4-1
Expanded Operating Mode ............................................................... 4-1
Special Test Mode ............................................................................. 4-1
Special Bootstrap Mode .................................................................... 4-1
On-Chip Memory ....................................................................................... 4-2
Mapping Allocations .......................................................................... 4-2
Memory Map ..................................................................................... 4-3
RAM .......................................................................................... 4-3
Bootloader ROM ....................................................................... 4-4
EEPROM ................................................................................... 4-4
Registers ........................................................................................... 4-4
System Initialization ................................................................................... 4-6
Mode Selection .................................................................................. 4-7
HPRIO Register ........................................................................ 4-8
Initialization ........................................................................................ 4-9
CONFIG Register ...................................................................... 4-9
INIT Register ........................................................................... 4-10
OPTION Register .................................................................... 4-11
OPT2 Register ........................................................................ 4-12
Block Protect Register (BPROT) ............................................. 4-13
EEPROM and CONFIG Register ............................................................ 4-14
EEPROM ......................................................................................... 4-14
EEPROM Programming .......................................................... 4-14
EEPROM Bulk Erase .............................................................. 4-15
EEPROM Row Erase .............................................................. 4-15
EEPROM Byte Erase .............................................................. 4-16
PPROG EEPROM Programming Control Register ......................... 4-16
CONFIG Register Programming ..................................................... 4-17
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TABLE OF CONTENTS
Paragraph
4.5
4.5.1
4.5.2
4.5.3
(Continued)
Title
Page
Chip Selects ............................................................................................ 4-18
Program Chip Select ....................................................................... 4-18
I/O Chip Selects .............................................................................. 4-18
General-Purpose Chip Select .......................................................... 4-19
SECTION 5 RESETS AND INTERRUPTS
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10
5.2.11
5.3
5.3.1
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.5
5.5.1
5.5.2
Resets ....................................................................................................... 5-1
Power-On Reset ................................................................................ 5-1
External Reset (RESET) ................................................................... 5-1
Computer Operating Properly (COP) Reset ...................................... 5-2
Clock Monitor Reset .......................................................................... 5-2
OPTION Register .............................................................................. 5-3
CONFIG Register .............................................................................. 5-4
Effects of Reset ......................................................................................... 5-4
Central Processing Unit ..................................................................... 5-5
Memory Map ..................................................................................... 5-5
Parallel I/O ......................................................................................... 5-5
Timer ................................................................................................. 5-5
Real-Time Interrupt (RTI) .................................................................. 5-5
Pulse Accumulator ............................................................................ 5-6
Computer Operating Properly (COP) ................................................ 5-6
Serial Communications Interface (SCI) ............................................. 5-6
Serial Peripheral Interface (SPI) ........................................................ 5-6
Analog-to-Digital Converter ............................................................... 5-6
System .............................................................................................. 5-6
Reset and Interrupt Priority ....................................................................... 5-6
Highest Priority Interrupt and Miscellaneous Register ...................... 5-7
Interrupts ................................................................................................... 5-8
Interrupt Recognition and Register Stacking ..................................... 5-9
Non-Maskable Interrupt Request (XIRQ) ........................................ 5-10
Illegal Opcode Trap ......................................................................... 5-10
Software Interrupt ............................................................................ 5-11
Maskable Interrupts ......................................................................... 5-11
Reset and Interrupt Processing ....................................................... 5-11
Low Power Operation .............................................................................. 5-16
WAIT ............................................................................................... 5-17
STOP ............................................................................................... 5-17
SECTION 6 PARALLEL INPUT/OUTPUT
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6.1
Port A ........................................................................................................ 6-1
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