Z8051 Series 8-Bit Microcontrollers
Z51F0811
Product Specification
PS029602-0212
PRELIMINARY
Copyright ©2012 Zilog
®
, Inc. All rights reserved.
www.zilog.com
Z51F0811
Product Specification
ii
Warning:
DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-
cal component is any component in a life support device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2012 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8051 is a trademark or registered trademark of Zilog, Inc. All other product or service names are the
property of their respective owners.
PS029602-0212
PRELIMINARY
Z51F0811
Product Specification
iii
Revision History
Each instance in this document’s revision history reflects a change from its previous edi-
tion. For more details, refer to the corresponding page(s) or appropriate links furnished in
the table below.
Revision
Level
Description
02
01
Removed references to SOP, LQFP packages.
Original Zilog issue.
Date
Feb
2012
Jan
2012
Page
All
All
PS029602-0212
PRELIMINARY
Revision History
Z51F0811
Product Specification
Table of Contents
Z51F0811 ........................................................................................................................................... 12
1. Overview ........................................................................................................................................ 12
1.1 Description ............................................................................................................................... 12
1.2 Features ................................................................................................................................... 13
1.3 Ordering Information ................................................................................................................ 14
1.3.1 Part Number Suffix Designation ........................................................................................ 14
1.4 Development Tools .................................................................................................................. 15
1.4.1 Compiler ........................................................................................................................... 15
1.4.2 OCD emulator and debugger ............................................................................................ 15
1.4.3 Programmer ...................................................................................................................... 15
2. Block Diagram ................................................................................................................................ 16
3. Pin Assignment .............................................................................................................................. 17
4. Package Diagram ........................................................................................................................... 21
5. Pin Description ............................................................................................................................... 25
6. Port Structures ............................................................................................................................... 26
6.1 General Purpose I/O Port ......................................................................................................... 26
6.2 External Interrupt I/O Port ........................................................................................................ 27
7. Electrical Characteristics ................................................................................................................ 28
7.1 Absolute Maximum Ratings ...................................................................................................... 28
7.2 Recommended Operating Conditions ...................................................................................... 28
7.3 A/D Converter Characteristics .................................................................................................. 29
7.4 Analog Comparator Characteristics.......................................................................................... 29
7.5 Voltage Dropout Converter Characteristics .............................................................................. 30
7.6 Power-On Reset Characteristics .............................................................................................. 31
7.7 Brown Out Detector Characteristics ......................................................................................... 31
7.8 Internal RC Oscillator Characteristics ....................................................................................... 32
7.9 Ring-Oscillator Characteristics ................................................................................................. 32
7.10 PLL Characteristics ................................................................................................................ 32
7.11 DC Characteristics ................................................................................................................. 33
7.12 AC Characteristics ................................................................................................................. 34
7.13 SPI Characteristics ................................................................................................................. 35
7.14 Typical Characteristics ........................................................................................................... 36
8. Memory .......................................................................................................................................... 37
8.1 Program Memory ..................................................................................................................... 37
8.2 Data Memory............................................................................................................................ 39
8.3 EEPROM Data Memory ........................................................................................................... 41
8.4 SFR Map .................................................................................................................................. 42
8.4.1 SFR Map Summary .......................................................................................................... 42
8.4.2 Compiler Compatible SFR ................................................................................................ 42
9. I/O Ports ......................................................................................................................................... 45
9.1 I/O Ports ................................................................................................................................... 45
9.2 Port Register ............................................................................................................................ 45
9.2.1 Data Register (Px) ............................................................................................................ 45
9.2.2 Direction Register (PxIO) .................................................................................................. 45
PS029602-0212
PRELIMINARY
1
Z51F0811
Product Specification
9.2.3 Pull-up Resistor Selection Register (PxPU) ...................................................................... 45
9.2.4 Open-drain Selection Register (PxOD) ............................................................................. 45
9.2.5 Debounce Enable Register (PxDB) ................................................................................... 45
9.2.6 Pin Change Interrupt Enable Register (PCI0) ................................................................... 45
9.2.7 Port Selection Register (PSRx) ......................................................................................... 46
9.2.8 Register Map..................................................................................................................... 46
9.3 Px Port ..................................................................................................................................... 46
9.3.1 Px Port Description ........................................................................................................... 46
9.3.2 Register description for Px ................................................................................................ 46
9.4 Port RESET Noise Canceller ................................................................................................... 48
10. Interrupt Controller........................................................................................................................ 49
10.1 Overview ................................................................................................................................ 49
10.2 External Interrupt .................................................................................................................... 49
10.3 Block Diagram ........................................................................................................................ 51
10.4 Interrupt Vector Table............................................................................................................. 52
10.5 Interrupt Sequence ................................................................................................................. 52
10.6 Effective Timing after Controlling Interrupt bit ......................................................................... 54
10.7 Multi Interrupt ......................................................................................................................... 55
10.8 Interrupt Enable Accept Timing .............................................................................................. 56
10.9 Interrupt Service Routine Address .......................................................................................... 56
10.10 Saving/Restore General-Purpose Registers ......................................................................... 56
10.11 Interrupt Timing .................................................................................................................... 57
10.12 Interrupt Register Overview .................................................................................................. 58
10.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3, IE4, IE5) ................................................... 58
10.12.2 Interrupt Priority Register (IP, IP1) ................................................................................ 58
10.12.3 External Interrupt Flag Register (EIFLAG) .................................................................... 58
10.12.4 External Interrupt Edge Register (EIEDGE) .................................................................. 58
10.12.5 External Interrupt Polarity Register (EIPOLA) ............................................................... 58
10.12.6 External Interrupt Enable Register (EIENAB) ................................................................ 58
10.12.7 External Interrupt Both Edge Enable Register (EIBOTH) .............................................. 58
10.12.8 Register Map................................................................................................................. 59
10.13 Interrupt Register Description ............................................................................................... 59
10.13.1 Register description for Interrupt ................................................................................... 59
11. Peripheral Hardware..................................................................................................................... 65
11.1 Clock Generator ..................................................................................................................... 65
11.1.1 Overview ......................................................................................................................... 65
11.1.2 Block Diagram................................................................................................................. 65
11.1.3 Register Map................................................................................................................... 66
11.1.4 Clock Generator Register description ............................................................................. 66
11.1.5 Register description for Clock Generator ........................................................................ 66
11.2 BIT ......................................................................................................................................... 68
11.2.1 Overview ......................................................................................................................... 68
11.2.2 Block Diagram................................................................................................................. 68
11.2.3 Register Map................................................................................................................... 68
11.2.4 Bit Interval Timer Register description............................................................................. 69
11.2.5 Register description for Bit Interval Timer ....................................................................... 69
11.3 WDT ....................................................................................................................................... 70
11.3.1 Overview ......................................................................................................................... 70
PS029602-0212
PRELIMINARY
2
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