LCMXO2280C-4BN256C datasheet, PDF

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LCMXO2280C-4BN256C: Descriptionfpga - field programmable gate array 2280 luts 211 I/O 1.8/2.5/3.3V -4 spd; Categorysemiconductor Other integrated circuit (IC); File Size8MB，244 Pages; ManufacturerAll Sensors; Environmental Compliance

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LCMXO2280C-4BN256C Overview

fpga - field programmable gate array 2280 luts 211 I/O 1.8/2.5/3.3V -4 spd

LCMXO2280C-4BN256C Parametric

Parameter Name	Attribute value
Manufacture	Lattice
Product Category	FPGA - Field Programmable Gate Array
RoHS	Yes
Produc	MachXO
Number of Logic Elements	2280
Number of Logic Array Blocks - LABs	285
Total Memory	35.3 kbi
Number of I/Os	211
Operating Supply Voltage	1.8 V, 2.5 V, 3.3 V
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	CABGA
Distributed RAM	7.7 kbi
Embedded Block RAM - EBR	27.6 kbi
Minimum Operating Temperature	0 C
Operating Supply Curre	23 mA
Packaging	Tray
Factory Pack Quantity	119

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MachXO Family Handbook

HB1002 Version 02.7, October 2011

MachXO Family Handbook

Table of Contents

October 2011

Section I. MachXO Family Data Sheet

Introduction

Features ............................................................................................................................................................. 1-1

Introduction ........................................................................................................................................................ 1-1

Architecture

Architecture Overview ........................................................................................................................................ 2-1

PFU Blocks ............................................................................................................................................... 2-3

Slice .......................................................................................................................................................... 2-3

Routing...................................................................................................................................................... 2-6

Clock/Control Distribution Network .................................................................................................................... 2-7

sysCLOCK Phase Locked Loops (PLLs) .................................................................................................. 2-9

sysMEM Memory ............................................................................................................................................. 2-10

PIO Groups ...................................................................................................................................................... 2-14

PIO .......................................................................................................................................................... 2-14

sysIO Buffer ..................................................................................................................................................... 2-15

sysIO Buffer Banks ................................................................................................................................. 2-18

Hot Socketing................................................................................................................................................... 2-20

Sleep Mode ...................................................................................................................................................... 2-21

SLEEPN Pin Characteristics ................................................................................................................... 2-21

Oscillator .......................................................................................................................................................... 2-21

Configuration and Testing ................................................................................................................................ 2-21

IEEE 1149.1-Compliant Boundary Scan Testability................................................................................ 2-21

Device Configuration............................................................................................................................... 2-22

Density Shifting ................................................................................................................................................ 2-23

DC and Switching Characteristics

Absolute Maximum Ratings ............................................................................................................................... 3-1

Recommended Operating Conditions

............................................................................................................... 3-1

MachXO256 and MachXO640 Hot Socketing Specifications............................................................................. 3-1

MachXO1200 and MachXO2280 Hot Socketing Specifications......................................................................... 3-2

DC Electrical Characteristics.............................................................................................................................. 3-2

Supply Current (Sleep Mode)............................................................................................................................. 3-3

Supply Current (Standby)................................................................................................................................... 3-3

Initialization Supply Current ............................................................................................................................... 3-4

Programming and Erase Flash Supply Current ................................................................................................. 3-5

sysIO Recommended Operating Conditions...................................................................................................... 3-6

sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-7

sysIO Differential Electrical Characteristics ....................................................................................................... 3-8

LVDS......................................................................................................................................................... 3-8

LVDS Emulation........................................................................................................................................ 3-8

BLVDS ...................................................................................................................................................... 3-9

LVPECL .................................................................................................................................................. 3-10

RSDS ...................................................................................................................................................... 3-11

Typical Building Block Function Performance.................................................................................................. 3-12

Register-to-Register Performance .......................................................................................................... 3-12

Derating Logic Timing ...................................................................................................................................... 3-12

MachXO External Switching Characteristics.................................................................................................... 3-13

MachXO Internal Timing Parameters............................................................................................................... 3-14

MachXO Family Timing Adders ....................................................................................................................... 3-15

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

Lattice Semiconductor

Table of Contents

MachXO Family Handbook

sysCLOCK PLL Timing .................................................................................................................................... 3-16

Flash Download Time ...................................................................................................................................... 3-17

JTAG Port Timing Specifications ..................................................................................................................... 3-17

Switching Test Conditions................................................................................................................................ 3-19

Pinout Information

Signal Descriptions ............................................................................................................................................ 4-1

Pin Information Summary................................................................................................................................... 4-2

Power Supply and NC........................................................................................................................................ 4-3

Power Supply and NC (Cont.)............................................................................................................................ 4-4

LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP ................................................................. 4-5

LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP ............................................................. 4-8

LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA.............................................................. 4-11

LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 132 csBGA ..................................... 4-14

LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 144 TQFP....................................... 4-17

LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections: 256 caBGA / 256 ftBGA ................. 4-20

LCMXO2280 Logic Signal Connections: 324 ftBGA ........................................................................................ 4-26

Thermal Management ...................................................................................................................................... 4-36

For Further Information ........................................................................................................................... 4-36

Ordering Information

Part Number Description.................................................................................................................................... 5-1

Ordering Information .......................................................................................................................................... 5-1

Conventional Packaging ........................................................................................................................... 5-2

Conventional Packaging ........................................................................................................................... 5-5

Lead-Free Packaging................................................................................................................................ 5-7

Lead-Free Packaging.............................................................................................................................. 5-10

Supplemental Information

For Further Information ...................................................................................................................................... 6-1

MachXO Family Data Sheet Revision History

Revision History ................................................................................................................................................. 7-1

Section II. MachXO Family Technical Notes

MachXO sysIO Usage Guide

Introduction ........................................................................................................................................................ 8-1

sysIO Buffer Overview .............................................................................................................................. 8-1

Supported sysIO Standards ...................................................................................................................... 8-1

sysIO Banking Scheme............................................................................................................................. 8-2

CCIO

(1.2V/1.5V/1.8V/2.5V/3.3V) ............................................................................................................ 8-4

CCAUX

(3.3V) ........................................................................................................................................... 8-4

Mixed Voltage Support in a Bank.............................................................................................................. 8-4

sysIO Standards Supported in Each Bank................................................................................................ 8-5

LVCMOS Buffer Configurations ......................................................................................................................... 8-5

Programmable PULLUP/PULLDOWN/BUSKEEPER ............................................................................... 8-5

Programmable Drive ................................................................................................................................. 8-6

Programmable Slew Rate ......................................................................................................................... 8-6

Open-Drain Control ................................................................................................................................... 8-6

Programmable PCICLAMP ....................................................................................................................... 8-6

5V Input Interface Using the PCI Clamp Diode......................................................................................... 8-6

Software sysIO Attributes................................................................................................................................... 8-8

IO_TYPE ................................................................................................................................................... 8-8

OPENDRAIN............................................................................................................................................. 8-9

DRIVE ....................................................................................................................................................... 8-9

PULLMODE .............................................................................................................................................. 8-9

PCICLAMP................................................................................................................................................ 8-9

SLEWRATE ............................................................................................................................................ 8-10

Lattice Semiconductor

Table of Contents

MachXO Family Handbook

LOC......................................................................................................................................................... 8-10

Design Considerations and Usage................................................................................................................... 8-10

Banking Rules ......................................................................................................................................... 8-10

Zero Hold Time ....................................................................................................................................... 8-10

Fast Output Path ..................................................................................................................................... 8-10

Dedicated Pins ........................................................................................................................................ 8-10

Differential I/O Implementation................................................................................................................ 8-11

Technical Support Assistance.......................................................................................................................... 8-11

Revision History ............................................................................................................................................... 8-12

Appendix A. HDL Attributes for Synplify

and Precision

RTL Synthesis ........................................................ 8-13

VHDL Synplify/Precision RTL Synthesis................................................................................................. 8-13

Verilog Synpilfy ....................................................................................................................................... 8-15

Verilog Precision RTL Synthesis............................................................................................................. 8-16

Appendix B. sysIO Attributes Using the ispLEVER Preference Editor or



Diamond Spreadsheet View ....................................................................................................................... 8-17

Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-19

IOBUF ..................................................................................................................................................... 8-19

LOCATE.................................................................................................................................................. 8-19

Memory Usage Guide for MachXO Devices

Introduction ........................................................................................................................................................ 9-1

MachXO Device Memories ................................................................................................................................ 9-1

Utilizing IPexpress.............................................................................................................................................. 9-2

IPexpress Flow.......................................................................................................................................... 9-2

True Dual Port RAM (RAM_DP_TRUE) – EBR Based ........................................................................... 9-12

Pseudo Dual Port RAM (RAM_DP)- EBR Based.................................................................................... 9-21

Read Only Memory (ROM) – EBR Based............................................................................................... 9-23

First In First Out (FIFO, FIFO_DC) - EBR Based.................................................................................... 9-25

Distributed Single Port RAM (Distributed_SPRAM) – PFU Based.......................................................... 9-30

Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based 32

Distributed ROM (Distributed_ROM) – PFU Based ................................................................................ 9-35

Initializing Memory ........................................................................................................................................... 9-36

Initialization File Formats ........................................................................................................................ 9-36

Technical Support Assistance.......................................................................................................................... 9-37

Revision History ............................................................................................................................................... 9-38

Appendix A. Attribute Definitions...................................................................................................................... 9-39

MachXO sysCLOCK Design and Usage Guide

Introduction ...................................................................................................................................................... 10-1

MachXO Top Level View.................................................................................................................................. 10-1

sysCLOCK PLL ................................................................................................................................................ 10-1

Features ........................................................................................................................................................... 10-2

Functional Description...................................................................................................................................... 10-2

PLL Divider and Delay Blocks................................................................................................................. 10-2

PLL Inputs and Outputs .......................................................................................................................... 10-3

Dynamic Delay Control I/O Ports ............................................................................................................ 10-3

PLL Attributes.......................................................................................................................................... 10-4

MachXO PLL Primitive Definitions ................................................................................................................... 10-4

PLL Attributes Definitions................................................................................................................................. 10-5

Dynamic Delay Adjustment ..................................................................................................................... 10-7

MachXO PLL Usage in IPexpress.................................................................................................................... 10-8

Configuration Tab.................................................................................................................................... 10-9

Mode ....................................................................................................................................................... 10-9

Frequency Programming in Divider Mode for Advanced Users ............................................................ 10-11

Oscillator (OSCC) .......................................................................................................................................... 10-13

Clock/Control Distribution Network ................................................................................................................ 10-13

Lattice Semiconductor

Table of Contents

MachXO Family Handbook

Primary Clock Mux Connectivity ........................................................................................................... 10-14

Secondary Clock/CE/LSR Mux Connectivity......................................................................................... 10-15

Primary Clock and Secondary Clock/CE/LSR Distribution Network ..................................................... 10-15

Maximum Number of Secondary Clocks Available ........................................................................................ 10-16

Post Map Preference Editor Usage................................................................................................................ 10-16

Technical Support Assistance........................................................................................................................ 10-17

Revision History ............................................................................................................................................. 10-17

Appendix A. Lattice Diamond Design Software Screen Shots....................................................................... 10-18

Power Estimation and Management for MachXO Devices

Introduction ...................................................................................................................................................... 11-1

Power Supply Sequencing and Hot Socketing................................................................................................. 11-1

Recommended Power-up Sequence ...................................................................................................... 11-1

Power Calculator Hardware Assumptions........................................................................................................ 11-1

Power Calculator.............................................................................................................................................. 11-1

Power Calculator Equations.................................................................................................................... 11-1

Power Calculations ................................................................................................................................. 11-2

Starting the Power Calculator ................................................................................................................. 11-3

Creating a Power Calculator Project ....................................................................................................... 11-4

Power Calculator Main Window .............................................................................................................. 11-5

Power Calculator Wizard......................................................................................................................... 11-7

Power Calculator - Creating a New Project Without the NCD File........................................................ 11-10

Power Calculator - Creating a New Project with the NCD File.............................................................. 11-11

Power Calculator - Open Existing Project ............................................................................................. 11-13

Power Calculator - Importing Simulation File (VCD) to the Project....................................................... 11-14

Power Calculator - Importing Trace Report File (TWR) to the Project .................................................. 11-15

Activity Factor and Toggle Rate ..................................................................................................................... 11-16

Ambient and Junction Temperature and Airflow ................................................................................... 11-16

Managing Power Consumption ............................................................................................................. 11-17

Power Calculator Assumptions ............................................................................................................. 11-17

Technical Support Assistance........................................................................................................................ 11-18

Revision History ............................................................................................................................................. 11-18

MachXO JTAG Programming and Configuration User’s Guide

Introduction ...................................................................................................................................................... 12-1

Programming Overview.................................................................................................................................... 12-1

ispJTAG ........................................................................................................................................................... 12-2

TDO......................................................................................................................................................... 12-2

TDI .......................................................................................................................................................... 12-2

TMS......................................................................................................................................................... 12-2

TCK ......................................................................................................................................................... 12-3

Supply for JTAG .............................................................................................................................. 12-3

Download Cable Pinout........................................................................................................................... 12-3

BSDL Files .............................................................................................................................................. 12-3

Device Wake Up .............................................................................................................................................. 12-3

Software Options.............................................................................................................................................. 12-3

Preference Options ................................................................................................................................. 12-3

Configuring SRAM or Programming Flash.............................................................................................. 12-4

Technical Support Assistance.......................................................................................................................... 12-4

Revision History ............................................................................................................................................... 12-5

HDL Synthesis Coding Guidelines for Lattice Semiconductor FPGAs

Introduction ...................................................................................................................................................... 13-1

General Coding Styles for FPGA ..................................................................................................................... 13-1

Hierarchical Coding................................................................................................................................. 13-1

Design Partitioning .................................................................................................................................. 13-2

State Encoding Methodologies for State Machines ................................................................................ 13-3

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