PIC24F16KM204 FAMILY
PIC24F16KM204 Family
Silicon Errata and Data Sheet Clarification
The PIC24F16KM204 family devices that you have
received conform functionally to the current Device
Data Sheet (DS30003030B), except for the anomalies
described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC24F16KM204 family silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the issues
indicated in the last column of
Table 2
apply to the current silicon revision (A1).
5.
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
2.
3.
4.
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select
Programmer >
Reconnect.
b) For MPLAB X IDE, select
Window > Dash-
board
and click the
Refresh Debug Tool
Status
icon (
).
Depending on the development tool used, the
part number
and
Device Revision ID value
appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
Data Sheet clarifications and corrections start on
Page 5,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s pro-
grammers, debuggers, and emulation tools, which are
available at the Microchip corporate web site
(www.microchip.com).
The DEVREV values for the various PIC24F16KM204
family silicon revisions are shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
Revision ID for
Silicon
Revision
(2)
A0
A1
PIC24F16KM204
PIC24F08KM204
PIC24F16KM104
0000h
0001h
PIC24F16KM202
PIC24F08KM202
PIC24F16KM102
PIC24F08KM102
PIC24F08KM101
551Eh
5516h
550Eh
551Ah
5512h
550Ah
5502h
5500h
0000h
0001h
Revision ID for
Silicon
Revision
(2)
A0
A1
Part Number
Device ID
(1)
Part Number
Device ID
(1)
PIC24FV16KM204
PIC24FV08KM204
PIC24FV16KM104
PIC24FV16KM202
PIC24FV08KM202
PIC24FV16KM102
PIC24FV08KM102
PIC24FV08KM101
Note 1:
2:
551Fh
5517h
550Fh
551Bh
5513h
550Bh
5503h
5501h
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
Refer to the
“PIC24FXXKMXXX/KLXXX Flash Programming Specifications”
(DS30625) for detailed
information on Device and Revision IDs for your specific device.
2013-2017 Microchip Technology Inc.
DS80000552H-page 1
PIC24F16KM204 FAMILY
TABLE 2:
Module
SILICON ISSUE SUMMARY
Feature
Item
Number
1.
2.
3.
4.
5.
6.
7.
8.
9.
Issue Summary
Affected
Revisions
(1)
A0
A1
X
X
X
X
X
X
X
X
X
A/D Converter
A/D Converter
MCCP and
SCCP
MCCP and
SCCP
MCCP and
SCCP
MCCP and
SCCP
MCCP and
SCCP
Op Amp
Reset
Note 1:
—
—
Triggered
Operation
Compare
Mode
Compare
Mode
Compare
Mode
—
—
BOR
Excessive current consumption under certain conditions.
Device Reset when sampling upper guardband input.
TRSET bit does not function in retrigger operations.
Extra compare event in One-Shot mode under certain conditions.
Output compare synchronization does not occur correctly for the
first event.
Special Event Trigger postscaler does not work.
Unexpected 32-bit timer rollover under certain conditions.
Op amp output and digital output drivers may cause bus conflict.
Unexpected BOR events when BOR is disabled in Sleep mode.
X
X
X
X
X
X
X
X
X
Only those issues indicated in the last column apply to the current silicon revision.
DS80000552H-page 2
2013-2017 Microchip Technology Inc.
PIC24F16KM204 FAMILY
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A1).
4. Module: MCCP and SCCP
In One-Shot Output Compare mode, an addi-
tional compare event may occur, causing an
extra toggling of the OCx pin and an additional
interrupt event. This occurs whenever the value
of CCPxRA is 0000h, and after the trigger has
been cleared and the CCPxTMR is reset.
Work around
1. Module: A/D Converter
When low-power operation is enabled (LPEN bit
is set), the module may still consume high
current (approximately 90 µA) when the device
is in Sleep mode and after the conversion is
completed.
Work around
After conversions in Sleep mode are complete,
wake the device and disable the module.
Affected Silicon Revisions
A0
X
A1
X
A non-zero value of CCPxRA (e.g., 0001h)
prevents the additional compare event.
Affected Silicon Revisions
A0
X
A1
X
5. Module: MCCP and SCCP
Output compare synchronization of the OCx pin
to the module’s selected time base (enabled
when OENSYNC (CCPxCON2H<15>) =
1)
may
prevent output on the pin on the first time base
period after enabling the module. After the first
period, OCx pin events will appear correctly.
Work around
None.
Affected Silicon Revisions
A0
X
A1
X
2. Module: A/D Converter
Sampling and converting the upper V
DD
guard-
band rail input (AD1CHS<12:8> =
11100)
may
cause a device Reset. This can occur without
regard to any other operating conditions.
Work around
Do not use the upper guardband input.
Affected Silicon Revisions
A0
X
A1
X
6. Module: MCCP and SCCP
When the Special Event Trigger output is
selected (CCPxCON1H =
1),
the interrupt post-
scaler setting, selected by CCPxCON1H<11:8>,
has no effect. A Special Event Trigger will output
on each compare match event.
Work around
None.
Affected Silicon Revisions
A0
X
A1
X
3. Module: MCCP and SCCP
In retrigger operation, setting the TRSET bit
(CCPxSTATL<6>) may not properly cause a
retrigger event. All other available trigger
sources will cause a retrigger event as
described.
Work around
If the TRSET bit must be used for retrigger
operation, set the TRCLR bit (CCPxSTATL<5>)
prior to setting the TRSET bit.
Affected Silicon Revisions
A0
X
A1
X
2013-2017 Microchip Technology Inc.
DS80000552H-page 3
PIC24F16KM204 FAMILY
7. Module: MCCP and SCCP
The MCCP module may rollover at an incorrect
time when all of the following conditions are met:
• The module is configured in 32-bit operation
(T32 (CCPxCON1L<5>) =
1)
• The CCPxTMRH and CCPxPRH registers
are initialized with the same value
• The CCPxTMRL register is initialized with a
value higher than CCPxPRL
• The module is configured for a timer match
with no external synchronization source
(SYNC<4:0> (CCPxCON1H<4:0>) =
00000)
With the module configured this way, the MCCP
module will clear the CCPxTMRH/L register pair
and generate a timer rollover interrupt when
CCPxTMRL rolls over from FFFFh to 0000h,
regardless of the value of CCPxTMRH. The
expected behavior would be to roll over only
after reaching the expected timer rollover value
of FFFFFFFFh.
For example, if the module is initialized with the
following settings:
• CCPxTMRH = CCPxPRH = 1000h
• CCPxPRL = 0000h
• CCPxTMRL = 0001h
When the module is enabled, it will run until
CCPxTMR = 1000FFFFh, then roll over to zero
and generate an MCCP timer rollover interrupt.
Work around
None.
Affected Silicon Revisions
A0
X
A1
X
2.
8. Module: Op Amp
When op amp modules are enabled, a bus conflict
between the module’s analog driver and the digi-
tal I/O driver may result, causing an unexpected
voltage level and high-current consumption.
This is only seen when the TRISx bit associated
with the OAxOUT pin is cleared. This results in the
digital output driver being enabled and conflicting
with the op amp’s analog output driver.
Work around
When using an op amp module, ensure that the
TRISx bit associated with the OAxOUT pin is set
as an input (TRISx =
1)
to disable the digital
output driver.
Affected Silicon Revisions
A0
X
A1
X
9. Module: Reset
Under certain conditions, the device may
improperly perform a Brown-out Reset upon
wake-up from a Sleep mode. This has been
observed under two conditions:
1.
When the BOR is disabled in Sleep mode,
BOREN<1:0> (FPOR<1:0>) =
10,
a BOR
may occur when the device wakes from
Sleep, regardless of the supply voltage.
When the BOR is configured for software
control (BOREN<1:0> =
01),
the device
enters and wakes from Sleep normally
while the BOR is disabled in software,
SBOREN (RCON<13>) =
0.
However, if the
BOR was disabled prior to entering Sleep
mode and is subsequently enabled after
waking from Sleep, a BOR may occur
regardless of the supply voltage.
BOR functions normally when it is always
enabled or disabled (BOREN<1:0> =
11
or
00).
Work around
Do not use Sleep mode when BOREN<1:0> =
10.
If the BOR is to operate under software
control, always enable the HLVD module,
HLVDEN (HLVDCON<15>) =
1,
before enabling
the BOR in software (SBOREN =
1).
This proce-
dure activates the internal band gap reference
and assures its stability for the BOR circuit.
Affected Silicon Revisions
A0
X
A1
X
DS80000552H-page 4
2013-2017 Microchip Technology Inc.
PIC24F16KM204 FAMILY
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS30003030B):
Note:
Corrections are shown in
bold.
Where
possible, the original bold text formatting
has been removed for clarity.
2. Module: Electrical Characteristics
Table 27-17:
Operational Amplifier Specifica-
tions has had the Input Offset Voltage Max value
and Common-Mode Input Voltage Range Max
value updated, as shown below in
bold.
1. Module: Memory Organization
In Table 4-25: A/D Register Map, and in
Register 19-6: AD1CHITH, Register 19-8:
AD1CSSH and Register 19-10 AD1CTMENH,
respectively, it is incorrectly noted that bits 3 and
4 are not implemented on 20-pin devices. These
bits are implemented on 20-pin parts, and
instead, this note should apply to bits 1 and 2.
TABLE 27-17: OPERATIONAL AMPLIFIER SPECIFICATIONS
Standard Operating Conditions:
DC CHARACTERISTICS
Operating temperature
Typ
(1)
±2
—
1.8V to 3.6V (PIC24F16KM204)
2.0V to 5.5V (PIC24FV16KM204)
-40°C
T
A
+85°C for Industrial
-40°C
T
A
+125°C for Extended
Units
mV
mV
Comments
Param
No.
Sym
V
IOFF
V
ICM
Characteristic
Input Offset Voltage
Common-Mode Input
Voltage Range
Min
—
AV
SS
Max
±50
AV
DD
– 850
Note 1:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3. Module: 12-Bit A/D Converter with
Threshold Detect
The Note 2 references in Register 19-6:
AD1CHITH moved from CHH19 and CHH20 to
CHH17 and CHH18. The Table Footnote 2 now
reads “The CHH<18:17> bits are not implemented
in 20-pin devices”.
The Note 2 references in Register 19-8:
AD1CSSH moved from CSS19 and CSS20 to
CSS17 and CSS18. The Table Footnote 2
now reads “The CSS<18:17> bits are not
implemented in 20-pin devices”.
The Note 2 reference in Register 19-10:
AD1CTMENH moved from CTMEN19 and
CTMEN20 to CTMEN17 and CTMEN18. The
Table Footnote 2 now reads “The CTMEN<18:17>
bits are not implemented in 20-pin devices.”
4. Module: Timer1
The first sentence in the Timer1 introduction has
changed to the following:
The Timer1 module is a 16-bit timer which
operates as a free-running, interval timer/
counter.
2013-2017 Microchip Technology Inc.
DS80000552H-page 5
京公网安备 11010802033920号
EEWORLD
