EEWORLDEEWORLDEEWORLD

Part Number

Search

Q7.0-SMU2-32-20/30-AEC-LF

Description
Parallel - Fundamental Quartz Crystal,
CategoryPassive components    Crystal/resonator   
File Size293KB,1 Pages
ManufacturerJauch
Websitehttp://www.jauchusa.com/
Environmental Compliance
Download Datasheet Parametric View All

Q7.0-SMU2-32-20/30-AEC-LF Overview

Parallel - Fundamental Quartz Crystal,

Q7.0-SMU2-32-20/30-AEC-LF Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid7301594916
Reach Compliance Codecompliant
Other featuresAEC-Q200; AT-CUT; TF-16949
Ageing5 PPM/FIRST YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level100 µW
frequency stability0.003%
frequency tolerance20 ppm
JESD-609 codee2
load capacitance32 pF
Installation featuresSURFACE MOUNT
Nominal operating frequency7 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
physical size11.5mm x 4.8mm x 3.0mm
Series resistance25 Ω
surface mountYES
Terminal surfaceTin/Copper (Sn/Cu)
SMU2 · AEC-Q200
- 2 Pad Version, 11.5 x 4.8 mm
- AEC-Q200 qualified
- production certified according IATF 16949
- package height 3.0 mm max.
actual size
2011/65/EC
RoHS
RoHS compliant
Pb free
REACH
compliant
Conflict
mineral free
GENERAL DATA
TYPE
frequency range
frequency tolerance at 25 °C
load capacitance C
L
shunt capacitance C
O
storage temperature
shock resistance
drive level max.
aging
SMU2 AEC-Q200
4.0 ~ 33.0 MHz
27.0 ~ 60.0 MHz
(fund. AT-cut)
(3rd OT AT-cut)
ESR (SERIES RESISTANCE RS)
frequency
in MHz
4.0 ~ 5.999
6.0 ~ 6.999
7.0 ~ 7.999
8.0 ~ 8.999
9.0 ~ 13.999
14.0 ~ 33.000
27.0 ~ 60.000
(half sine pulse, 6.0 ms)
(100 µW recommended)
vibration
mode
fund. - AT
fund. - AT
fund. - AT
fund. - AT
fund. - AT
fund. - AT
3rd OT-AT
ESR max.
in ½
80
70
50
50
35
30
100
ESR typ.
in ½
60
35
25
25
15
10
60
±20 ppm / ±30 ppm / ±50 ppm
12 pF ~ 32.0 pF or series
< 5 pF
-40 °C ~ +125 °C
> 100 g
500 µW
< ±5 ppm first year
MARKING
frequency with load capacitance code
company code / date code / internal code
TABLE 1: FREQUENCY STABILITY VS. TEMPERATURE
±30 ppm
±50 ppm
±100 ppm
±150 ppm
Jan. Feb. Mar. Apr. May Jun. Jul. Aug. Sep. Oct. Nov. Dec.
2019 2023
2020 2024
2021 2025
2022 2026
a
n
A
N
b
p
B
P
c
q
C
Q
d
r
D
R
e
s
E
S
f
t
F
T
g
u
G
U
h
v
H
V
j
w
J
W
k
x
K
X
l
y
L
Y
m
z
M
Z
-20 °C ~ +70 °C
-40 °C ~ +85 °C
-40 °C ~ +105 °C
-40 °C ~ +125 °C
standard
available
STD.
T1
T2
T3
DIMENSIONS
3.8 max.
0.6
+0.2 / -0.1
12.5
±0.3
< 3.5°
< 3.5°
0.3 max.
max. 0.2
4.8 max.
3.0 max.
max. 0.2
4.4
±0.1
10.1 max.
11.5
±0.2
Z
Z
3.7
±0.3
5.5
±0.1
5.5
±0.1
top view
side view
side view
bottom view
2.0
±0.1
pad layout
in mm
ORDER INFORMATION
Q
Quartz
frequency
4.0 ~ 60.0 MHz
type
SMU2
load capacitance
12 pF ~ 32 pF
S for series
tolerance at
25 °C
20 = ±20 ppm
30 = ±30 ppm
50 = ±50 ppm
stability vs.
temp. range
30 = ±30 ppm
50 = ±50 ppm
100 = ±100 ppm
150 = ±150 ppm
option 1
blank = -20 °C ~ +70 °C
T1 = -40 °C ~ +85 °C
T2 = -40 °C ~ +105 °C
T3 = -40 °C ~ +125 °C
FU = for fundamental frequencies ≥ 20 MHz
3OT = 3rd overtone
AEC = AEC-Q200 qualified
Example: Q 25.0-SMU2-30-30/50-T2-FU-AEC-LF
(Suffix LF = RoHS compliant / Pb free)
20012021
Jauch Quartz GmbH • e-mail: info@jauch.de • full data can bedata can be found under:
info@jauch.com
full found under: www.jauch.com
All specifications are subject to change without notice
www.jauch.de | www.jauch.co.uk | www.jauch.fr | www.jauchusa.com
ispPAC10 In-System Programmable Simulator and Its Application
[b]Abstract[/b]: ispPAC10 is the latest in-system programmable analog circuit device launched by Lattice Corporation of the United States. It provides an effective new way for electronic circuit desig...
maker FPGA/CPLD
Analog integrated circuit EDA technology and design: simulation and layout examples
This book is one of the planned textbooks in the series of microelectronics and integrated circuit design. The whole book follows the full-custom design process of analog integrated circuits and intro...
arui1999 Download Centre
Recruiting sales representatives (Shanghai area)--Famous Korean encryption chip company
[font=Helvetica][size=14px]In order to expand its business in Shanghai, a famous Korean encryption chip company is now recruiting a sales representative (Shanghai area). [/size][/font] [font=Helvetica...
happyangliu Recruitment
Hello everyone, who can introduce the interface circuit between user interface circuit chip PBL38710 and CPLD?
The connection of PBL38710/1 in the user circuit is shown in Figure 3. The user's telephone is connected to OVP through the TIP and RING lines, and then connected to the TIPX and RINGX pins of PBL3871...
bhyangyong FPGA/CPLD
High-voltage, high-brightness LED driver
By Dave Priscak, Systems Applications Manager, Texas Instruments (TI) As countries move away from incandescent light bulbs and companies realize the energy savings that can be achieved by switching to...
德州仪器 Analogue and Mixed Signal
The process of WEBENCH design + a K-type thermocouple sensor circuit design
1. Design topic: Design of a K-type thermocouple sensor circuit Use webench software tool to design a K-type thermocouple sensor circuit 2. Design process Select thermocouple sensor on webench pageSta...
qwqwqw2088 Analogue and Mixed Signal

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1674  1552  1227  2483  61  34  32  25  50  2 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号