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EPM7512AEQC208-12N

Description
cpld - complex programmable logic devices cpld - max 7000 512 macro 176 ios
CategoryProgrammable logic devices    Programmable logic   
File Size960KB,64 Pages
ManufacturerAltera (Intel)
Environmental Compliance
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EPM7512AEQC208-12N Overview

cpld - complex programmable logic devices cpld - max 7000 512 macro 176 ios

EPM7512AEQC208-12N Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAltera (Intel)
Parts packaging codeQFP
package instructionPLASTIC, QFP-208
Contacts208
Reach Compliance Codeunknow
ECCN code3A991
Other features512 MACROCELLS; 32 LABS; CONFIGURABLE I/O OPERATION WITH 2.5 OR 3.3
maximum clock frequency71.9 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G208
JESD-609 codee3
JTAG BSTYES
length28 mm
Humidity sensitivity level3
Dedicated input times
Number of I/O lines176
Number of macro cells512
Number of terminals208
Maximum operating temperature70 °C
Minimum operating temperature
organize0 DEDICATED INPUTS, 176 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Encapsulate equivalent codeQFP208,1.2SQ,20
Package shapeSQUARE
Package formFLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)245
power supply2.5/3.3,3.3 V
Programmable logic typeEE PLD
propagation delay12 ns
Certification statusNot Qualified
Maximum seat height4.1 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width28 mm
MAX 7000A
®
Includes
MAX 7000AE
Programmable Logic
Device
Data Sheet
September 2003, ver. 4.5
Features...
High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
®
) architecture (see
Table 1)
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
Enhanced ISP features
Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
Pull-up resistor on I/O pins during in-system programming
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
Extended temperature range
f
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the
MAX 7000 Programmable Logic Device Family
Data Sheet
or the
MAX 7000B Programmable Logic Device Family Data Sheet.
Altera Corporation
DS-M7000A-4.5
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