MachXO2™ Family Data Sheet
DS1035 Version 02.1, June 2013
MachXO2 Family Data Sheet
Introduction
January 2013
Data Sheet DS1035
Features
Flexible Logic Architecture
Ultra Low Power Devices
•
•
•
•
Advanced 65 nm low power process
As low as 19 µW standby power
Programmable low swing differential I/Os
Stand-by mode and other power saving options
• Six devices with 256 to 6864 LUT4s and
19 to 335 I/Os
Flexible On-Chip Clocking
• Eight primary clocks
• Up to two edge clocks for high-speed I/O
interfaces (top and bottom sides only)
• Up to two analog PLLs per device with
fractional-n frequency synthesis
– Wide input frequency range (10 MHz to
400 MHz)
Non-volatile, Infinitely Reconfigurable
Instant-on – powers up in microseconds
Single-chip, secure solution
Programmable through JTAG, SPI or I
2
C
Supports background programming of non-vola-
tile memory
• Optional dual boot with external SPI memory
•
•
•
•
Embedded and Distributed Memory
• Up to 240 Kbits sysMEM™ Embedded Block
RAM
• Up to 54 Kbits Distributed RAM
• Dedicated FIFO control logic
On-Chip User Flash Memory
• Up to 256 Kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I
2
C and
JTAG interfaces
• Can be used as soft processor PROM or as
Flash memory
TransFR™ Reconfiguration
• In-field logic update while system operates
Enhanced System Level Support
• On-chip hardened functions: SPI, I
2
C, timer/
counter
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• One Time Programmable (OTP) mode
• Single power supply with extended operating
range
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming
Pre-Engineered Source Synchronous I/O
•
•
•
•
•
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRX2, DDRX4
Dedicated DDR/DDR2/LPDDR memory with
DQS support
Broad Range of Package Options
• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,
fpBGA, QFN package options
• Small footprint package options
– As small as 2.5x2.5mm
• Density migration supported
• Advanced halogen-free packaging
High Performance, Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
– PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1035
Introduction_01.6
Introduction
MachXO2 Family Data Sheet
Table 1-1. MachXO2™ Family Selection Guide
XO2-256
XO2-640
XO2-640U
1
XO2-1200
XO2-1200U
1
XO2-2000
XO2-2000U
1
XO2-4000
XO2-7000
LUTs
Distributed RAM (Kbits)
EBR SRAM (Kbits)
Number
of EBR SRAM
Blocks (9 Kbits/block)
UFM (Kbits)
HC
Device Options
2
256
2
0
0
0
HE
3
ZE
4
0
2
1
1
640
5
18
2
24
640
5
64
7
64
1280
10
64
7
64
1280
10
74
8
80
2112
16
74
8
80
2112
16
92
10
96
4320
34
92
10
96
6864
54
240
26
256
Number
of PLLs
Hardened Functions:
I
2
C
SPI
Timer/Counter
Packages
25
WLCSP
(2.5 x 2.5mm, 0.4mm)
32 QFN
6
(5 x 5mm, 0.5mm)
64
ucBGA
(4 x 4mm, 0.4mm)
100 TQFP
(14 x 14mm)
132 csBGA
(8 x
8mm,
0.5mm)
144 TQFP
(20 x 20mm)
184 csBGA
7
(8 x
8mm,
0.5mm)
256 caBGA
(14 x 14mm, 0.8mm)
256 ftBGA
(17 x 17mm, 1.0mm)
332 caBGA
(17 x 17mm, 0.8mm)
484 fpBGA
(23 x 23mm, 1.0mm)
5
0
2
1
1
1
2
1
1
1
2
1
1
I/Os
18
1
2
1
1
1
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
21
44
55
55
78
79
107
79
104
107
79
104
111
104
114
150
206
206
206
206
206
274
278
278
206
206
278
334
114
1. Ultra high I/O device.
2.
High performance with regulator – V
CC
= 2.5V, 3.3V
3.
High performance without regulator – V
CC
= 1.2V
4.
Low power without regulator – V
CC
= 1.2V
5.
WLCSP
package only available for ZE devices.
6. QFN package only available for HC and ZE devices.
7. 184 csBGA package only available for HE devices.
Introduction
The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from
256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature
Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-
engineered source synchronous I/O support, advanced configuration support including dual-boot capability and
hardened versions of commonly used functions such as SPI controller, I
2
C controller and timer/counter. These fea-
tures allow these devices to be used in low cost, high volume consumer and system applications.
The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has sev-
eral features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs
1-2
Introduction
MachXO2 Family Data Sheet
and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low
static power for all members of the family.
The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE)
devices. The ultra low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. Sim-
ilarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. HC
devices have an internal linear voltage regulator which supports external V
CC
supply voltages of 3.3V or 2.5V. ZE
and HE devices only accept 1.2V as the external V
CC
supply voltage. With the exception of power supply voltage
all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.
The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space
saving 2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the same
package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.
The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range
of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.
The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati-
bility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-
down and bus-keeper features are controllable on a “per-pin” basis.
A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may
be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-
ilar state machines.
The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These
devices can also configure themselves from external SPI Flash or be configured by an external master through the
JTAG test access port or through the I
2
C port. Additionally, MachXO2 devices support dual-boot capability (using
external Flash memory) and remote field upgrade (TransFR) capability.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the
MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice
design tools use the synthesis tool output along with the user-specified preferences and constraints to place and
route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into
the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of
reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft
core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increas-
ing their productivity.
1-3
MachXO2 Family Data Sheet
Architecture
June 2013
Data Sheet DS1035
Architecture Overview
The MachXO2 family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The
larger logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM
(EBRs). Figures 2-1 and 2-2 show the block diagrams of the various family members.
Figure 2-1. Top View of the MachXO2-1200 Device
Embedded Function
Block (EFB)
User Flash Memory
(UFM)
sysCLOCK PLL
On-chip Configuration
Flash Memory
sysMEM Embedded
Block RAM (EBR)
PIOs Arranged into
sysIO Banks
Programmable Function Units
with Distributed RAM (PFUs)
Note: MachXO2-256, and MachXO2-640/U are similar to MachXO2-1200. MachXO2-256 has a lower LUT count and no PLL or EBR blocks.
MachXO2-640 has no PLL, a lower LUT count and two EBR blocks. MachXO2-640U has a lower LUT count, one PLL and seven EBR blocks.
Figure 2-2. Top View of the MachXO2-4000 Device
Embedded
Function Block(EFB)
User Flash
Memory (UFM)
sysCLOCK PLL
On-chip Configuration
Flash Memory
PIOs Arranged into
sysIO Banks
sysMEM Embedded
Block RAM (EBR)
Programmable Function Units
with Distributed RAM (PFUs)
Note: MachXO2-1200U, MachXO2-2000/U and MachXO2-7000 are similar to MachXO2-4000. MachXO2-1200U and MachXO2-2000 have a lower LUT count,
one PLL, and eight EBR blocks. MachXO2-2000U has a lower LUT count, two PLLs, and 10 EBR blocks. MachXO2-7000 has a higher LUT count, two PLLs,
and 26 EBR blocks.
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1035
Architecture_01.6
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