LCMXO2-2000ZE-1MG132I datasheet, PDF

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LCMXO2-2000ZE-1MG132I: Descriptionfpga - field programmable gate array 2112 luts 105 IO 1.2V 1 spd; Categorysemiconductor Other integrated circuit (IC); File Size527KB，30 Pages; ManufacturerAll Sensors; Environmental Compliance

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LCMXO2-2000ZE-1MG132I Overview

fpga - field programmable gate array 2112 luts 105 IO 1.2V 1 spd

LCMXO2-2000ZE-1MG132I Parametric

Parameter Name	Attribute value
Manufacture	Lattice
Product Category	FPGA - Field Programmable Gate Array
RoHS	Yes
Produc	MachXO2
Number of Logic Elements	2112
Number of Logic Array Blocks - LABs	264
Total Memory	170 kbi
Number of I/Os	104
Operating Supply Voltage	1.2 V
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	BGA-132
Distributed RAM	16 kbi
Embedded Block RAM - EBR	74 kbi
Maximum Operating Frequency	133 MHz
Minimum Operating Temperature	- 40 C
Operating Supply Curre	82 uA
Packaging	Tray
Factory Pack Quantity	360
User Flash Memory - UFM	80 kbi

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MachXO2 Product Family Qualification Summary

Lattice Document # 25 – 106923

February 2013

Lattice Semiconductor Corporation Doc. #25-106923 Rev. F

INDEX

1.0 INTRODUCTION .................................................................................................................................................. 4

Table 1.1 MachXO2 Product-Package

THIS TABLE AND RED TEXT ON THIS PAGE WILL BE DELETEDError!

Bookmark

2.0 LATTICE PRODUCT QUALIFICATION PROGRAM .......................................................................................... 5

Figure 2.1: Lattice Standard Product Qualification Process Flow ............................................................................. 6

Table 2.2: Standard Qualification Testing ................................................................................................................. 8

3.0 QUALIFICATION DATA MACHXO2 PRODUCT FAMILY ................................................................................ 10

3.1 M

ACH

XO2 P

RODUCT

AMILY

IFE

(HTOL) D

ATA

...................................................................................................... 10

Table 3.1.1: MachXO2 Product Family Life Results ................................................................................................ 10

3.2 M

ACH

XO2 P

RODUCT

AMILY

IGH

EMPERATURE

ETENTION

(HTRX) D

ATA

............................................................. 12

Table 3.2.1: MachXO2 High Temperature Retention Results ................................................................................. 12

3.3 M

ACH

XO2 P

RODUCT

AMILY

LASH

NDURANCE

YCLING

ATA

.............................................................................. 13

Table 3.3.1: MachXO2 Flash Extended Endurance Results ................................................................................... 13

3.4 M

ACH

XO2 P

RODUCT

AMILY

– ESD

AND

ATCH

UP D

ATA

........................................................................................ 14

Table 3.4.1 MachXO2 ESD-HBM Data ................................................................................................................... 14

Table 3.4.2 MachXO2 ESD-MM Data ..................................................................................................................... 16

Table 3.4.3 MachXO2 ESD-CDM Data ................................................................................................................... 17

Table 3.4.4 MachXO2 I/O Latch Up >100mA @ HOT (105°C) Data ....................................................................... 19

Table 3.4.5 MachXO2 Vcc Latch Up >1.5X @ HOT (105°C) Data ......................................................................... 20

4.0 PACKAGE QUALIFICATION DATA FOR MACHXO2 PRODUCT FAMILY .................................................... 21

Table 4.0 Product-Package Qualification-By-Extension Matrix ............................................................................... 21

4.1 M

ACH

XO2 P

RODUCT

AMILY

URFACE

OUNT

RECONDITIONING

ESTING

............................................................... 22

Table 4.1.1 Surface Mount Precondition Data......................................................................................................... 22

4.2 M

ACH

XO2 P

RODUCT

AMILY

EMPERATURE

YCLING

ATA

...................................................................................... 23

Table 4.2.1: Temperature Cycling Data................................................................................................................... 23

4.3 M

ACH

XO2 P

RODUCT

AMILY

NBIASED

HAST D

ATA

................................................................................................ 24

Table 4.3.1: Unbiased HAST Data .......................................................................................................................... 24

4.4 M

ACH

XO2 P

RODUCT

AMILY

THB: B

IASED

HAST D

ATA

........................................................................................... 25

Table 4.4.1: Biased HAST Data .............................................................................................................................. 25

4.5 M

ACH

XO2 P

RODUCT

AMILY

IGH

EMPERATURE

TORAGE

IFE

(HTSL) ................................................................. 26

Table 4.5.1: MachXO2 High Temperature Storage Life Results ............................................................................. 26

5.0 MACHXO2 PROCESS RELIABILITY WAFER LEVEL REVIEW ..................................................................... 27

Table 5.1 – Wafer Level Reliability (WLR) Results .................................................................................................. 27

6.0 MACHXO2 SOFT ERROR RATE DATA ........................................................................................................... 28

Table 6.1 - MachXO2 MEASURED FITs / Mb ......................................................................................................... 28

7.0 MACHXO2 ADDITIONAL FAMILY DATA......................................................................................................... 29

Table 7.1: MachXO2 Package Assembly Data – BGA & TQFP ............................................................................ 29

8.0 REVISION HISTORY ......................................................................................................................................... 30

Table 8.1: MachXO2 Product Family Qualification Summary revisions .................................................................. 30

Lattice Semiconductor Corporation Doc. #25-106923 Rev. F

1.0 INTRODUCTION

The MachXO2 family of ultra-low power, instant-on, non-volatile PLDs has six devices with densities ranging

from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices

feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops

(PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot

capability and hardened versions of commonly used functions such as SPI controller, I2C controller and

timer/counter. These features allow these devices to be used in low cost, high volume consumer and system

applications.

The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has

several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip

PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting

in low static power for all members of the family.

The MachXO2 devices are available in three options – ultra low power (ZE) and high performance (HC and HE)

devices. The ultra-low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest.

Similarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the

fastest. HC devices have an internal linear voltage regulator which supports external VCC supply voltages of

3.3V or 2.5V. ZE and HE devices only accept 1.2V as the external VCC supply voltage. With the exception of

power supply voltage all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible

with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space

saving 2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the

same package.

INDEX Return

Lattice Semiconductor Corporation Doc. #25-106923 Rev. F

2.0 LATTICE PRODUCT QUALIFICATION PROGRAM

Lattice Semiconductor Corp. maintains a comprehensive reliability qualification program to assure that each

product achieves its reliability goals. After initial qualification, the continued high reliability of Lattice products is

assured through ongoing monitor programs as described in Lattice Semiconductor’s Reliability Monitor Program

Procedure (Doc. #70-101667). All product qualification plans are generated in conformance with Lattice

Semiconductor’s Qualification Procedure (Doc. #70-100164) with failure analysis performed in conformance with

Lattice Semiconductor’s Failure Analysis Procedure (Doc. #70-100166). Both documents are referenced in

Lattice Semiconductor’s Quality Assurance Manual, which can be obtained upon request from a Lattice

Semiconductor sales office. Figure 2.1 shows the Product Qualification Process Flow.

If failures occur during qualification, an 8D process is used to find root cause and eliminate the failure mode

from the design, materials, or process. The effectiveness of any fix or change is validated through additional

testing as required. Final testing results are reported in the qualification reports.

Failure rates in this reliability report are expressed in FITs. Due to the very low failure rate of integrated circuits,

it is convenient to refer to failures in a population during a period of 10 device hours; one failure in 10 device

hours is defined as one FIT.

Product families are qualified based upon the requirements outlined in Table 2.2. In general, Lattice

Semiconductor follows the current Joint Electron Device Engineering Council (JEDEC) and Military Standard

testing methods. Lattice automotive products are qualified and characterized to the Automotive Electronics

Council (AEC) testing requirements and methods. Product family qualification will include products with a wide

range of circuit densities, package types, and package lead counts. Major changes to products, processes, or

vendors require additional qualification before implementation.

The MachXO2 family is the third generation FPGA product family and first 65 nm (CS200FL) Flash Technology

based product offering. The Lattice Semiconductor MachXO2 FPGA product family qualification efforts are

based on the first MachXO2 devices in the family per the Lattice Semiconductor Qualification Procedure,

doc#70-100164.

Lattice Semiconductor maintains a regular reliability monitor program. The current Lattice Reliability Monitor

Report can be found at

www.latticesemi.com/lit/docs/qa/product_reliability_monitor.pdf

INDEX Return

Lattice Semiconductor Corporation Doc. #25-106923 Rev. F

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