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7035L20PF8

Description
sram 16k X 16 dual port
Categorysemiconductor    Other integrated circuit (IC)   
File Size666KB,19 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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7035L20PF8 Overview

sram 16k X 16 dual port

7035L20PF8 Parametric

Parameter NameAttribute value
ManufactureIDT (Integrated Device Technology)
Product CategorySRAM
RoHSN
Package / CaseTQFP-100
PackagingReel
Factory Pack Quantity750
HIGH-SPEED
8K x 18 DUAL-PORT
STATIC RAM
IDT7035S/L
Features
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT7035S
Active: 800mW (typ.)
Standby: 5mW (typ.)
– IDT7035L
Active: 800mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT7035 easily expands data bus width to 36 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available. See ordering information
Functional Block Diagram
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
BUSY
L
(1,2)
I/O
9R
-I/O
17R
I/O
Control
I/O
Control
I/O
0R
-I/O
8R
BUSY
R
(1,2)
A
12L
A
0L
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
A
12R
A
0R
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
INT
R
(2)
4088 drw 01
M/
S
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
JUNE 2015
1
©2015 Integrated Device Technology, Inc.
DSC 4088/10
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