Sets the drive strength of the output drivers and feedback inputs to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or eHSTL/HSTL (LOW)
compatible. Used in conjuction with V
DDQ
to set the interface levels.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock (has internal pull-up).
3-level inputs for selecting 1 of 18 skew taps or frequency functions (See Control Summary table)
3-level inputs for selecting 1 of 18 skew taps or frequency functions (See Control Summary table)
Selects appropriate oscillator circuit based on anticipated frequency range (See Programmable Skew Range table)
3-level inputs for feedback input divider selection (See Divide Selection table)
PLL enable/disable control. Set LOW for normal operation. When
PLL_EN
is HIGH, the PLL is disabled and REF
[1:0]
goes to all outputs.
Power down control. When
PD
is LOW, the inputs are disabled and internal switching is stopped. OMODE selects whether the outputs
are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/
HIGH, the nQ and QFB are stopped in a HIGH/LOW state, while the
nQ
and
QFB
are stopped in a LOW/HIGH state. When OMODE
is LOW, the outputs are tri-stated. Set
PD
HIGH for normal operation.
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the
inputs. (For more information on application specific use of the LOCK pin, please see AN237.)
Output disable control. Determines the outputs' disable state. Used in conjunction with
nsOE
and
PD.
(See Output Enable/Disable and
Powerdown tables.)
Power supply for output buffers. When using 2.5V LVTTL, V
DDQ
should be connected to V
DD.
Power supply for phase locked loop, lock output, inputs, and other internal circuitry
Ground
QFB
QFB
nQ
nQ
RxS
TxS
PE
nF
[2:0]
FBF
[2:0]
FS
DS
[1:0]
PLL_EN
PD
O
O
O
O
I
I
I
I
I
I
I
I
I
Adjustable
(2)
Adjustable
(2)
Adjustable
(2)
Adjustable
(2)
3-Level
(3)
3-Level
(3)
LVTTL
(1)
3-Level
(3)
3-Level
(3)
LVTTL
3-Level
(3)
LVTTL
(1)
LVTTL
(1)
LOCK
OMODE
V
DDQ
V
DD
GND
O
I
LVTTL
LVTTL
(1)
PWR
PWR
PWR
NOTES:
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept the 1.8V LVTTL signals as
well.
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V
DDQ
voltage.
3. 3-level inputs are static inputs and must be tied to V
DD
or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
OUTPUT ENABLE/DISABLE
nsOE
L
H
H
OMODE
X
L
H
Output
Normal Operation
Tri-State
Gated
(1)
POWERDOWN
PD
H
L
L
OMODE
X
L
H
Output
Normal Operation
Tri-State
Gated
(1)
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ
is stopped in a HIGH/LOW state while the
nQ
is stopped at a LOW/HIGH state.
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ
and QFB are stopped in a HIGH/LOW state, while the
adjustable to compensate for PCB trace delays, backplane propagation
delays or to accommodate requirements for special timing relationships
between clocked components. Skew is selectable as a multiple of a time
unit (t
U
) which ranges from 250ps to 1.25ns (see Programmable Skew
Range and Resolution Table). There are 18 skew/divide configurations
available for each output pair. These configurations are chosen by the
nF
[2:0]
/FBF
[2:0]
control pins. In order to minimize the number of control
pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for
but not restricted to hard-wiring. Undriven 3-level inputs default to the
MID level. The Control Summary Table shows how to select specific
skew taps by using the nF
[2:0]
/FBF
[2:0]
control pins.
EXTERNAL DIFFERENTIAL FEEDBACK
By providing a dedicated external differential feedback, the IDT5T9110
gives users flexibility with regard to skew adjustment. The FB and
FB/
V
REF2
signals are compared with the input REF
[1:0]
and
REF
[1:0]
/V
REF
[1:0]
signals at the phase detector in order to drive the VCO. Phase differ-
ences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW
Timing Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1,2)
Skew Adjustment Range
(3)
Max Adjustment:
±8.75ns
±157.5°
±43.75%
Example 1, F
NOM
= 50MHz
Example 2, F
NOM
= 75MHz
Example 3, F
NOM
= 100MHz
Example 4, F
NOM
= 150MHz
Example 5, F
NOM
= 200MHz
Example 6, F
NOM
= 250MHz
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
—
—
—
±4.375ns
±157.5°
±43.75%
—
—
t
U
= 0.625ns
t
U
= 0.417ns
t
U
= 0.313ns
t
U
= 0.25ns
ns
Phase Degrees
% of Cycle Time
1/(16 x F
NOM
)
50 to 125MHz
FS = HIGH
1/(16 x F
NOM
)
100 to 250MHz
Comments
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at nQ and
nQ
outputs
when they are operated in their undivided modes. The frequency appearing at the REF
[1:0]
and
REF
[1:0]
/V
REF[1:0]
and FB and
FB/V
REF2
inputs will be F
NOM
when the QFB and
QFB
are undivided and DS
[1:0]
= MM. The frequency of the REF
[1:0]
and
REF
[1:0]
/V
REF[1:0]
and FB and
FB/V
REF2
inputs will be F
NOM
/2 or F
NOM
/4 when the part is configured
for frequency multiplication by using a divided QFB and
QFB
and setting DS
[1:0]
= MM. Using the DS[
1:0
] inputs allows a different method for frequency multiplication (see Divide
Selection Table).
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed QFB and
QFB
output is used for feedback, then adjustment range will be greater.
For example if a 4t
U
skewed output is used for feedback, all other outputs will be skewed –4t
U
in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’
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