3.3 V 1:11 LVCMOS Zero Delay
Clock Generator
NRND – Not Recommend for New Designs
The MPC93R52 is a 3.3V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output frequencies up
to 240MHz and output skews lower than 200ps, the device meets the needs of
most demanding clock applications.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Configurable 11 Outputs LVCMOS PLL Clock Generator
Fully Integrated PLL
Wide Range of Output Clock Frequency of 16.67MHz to 240MHz
Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 3
2, 2
3,
1
3, and 1
2
3.3 V LVCMOS Compatible
Maximum Output Skew of 200ps
Supports Zero-Delay Applications
Designed for High-Performance Telecom, Networking and Computing
Applications
32-Lead LQFP Package
32-Lead Pb-free Package Available
Ambient Temperature Range – 0°C to +70°C
Pin and Function Compatible to the MPC952
NRND – Not Recommend for New Designs
Use replacement part ICS87952
MPC93R52
NRND
DATASHEET
MPC93R52
LOW VOLTAGE
3.3 V LVCMOS 1:11
CLOCK GENERATOR
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
The MPC93R52 is a fully 3.3 V compatible PLL clock generator and clock driv-
er. The device has the capability to generate output clock signals of 16.67MHz to
240MHz from external clock sources. The internal PLL is optimized for its frequency range and does not require external look
filter components. One output of the MPC93R52 has to be connected to the PLL feedback input FB_IN to close the external PLL
feedback path. The output divider of this output setting determines the PLL frequency multiplication factor. This multiplication fac-
tor, F_RANGE and the reference clock frequency must be selected to situate the VCO in its specified lock range. The frequency
of the clock outputs can be configured individually for all three output banks by the FSELx pins supporting systems with different
but phase-aligned clock frequencies.
The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50
transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC93R52 is package in a 32 ld LQFP.
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
MPC93R52 REVISION 5 JANUARY 7, 2013
1
©2013 Integrated Device Technology, Inc.
MPC93R52 Data Sheet
3.3 V 1:11 LVCMOS Zero Delay Clock Generator
CCLK
CCLK
Ref
FB
PLL
Bank A
1
2
1
0
6
4
2
1
0
QA0
QA1
VCO 0
QA2
QA3
QA4
Bank B
QB0
QB1
FB_IN
PLL_EN
200 - 480 MHz
F_RANGE
1
0
FSELA
FSELB
QB2
QB3
Bank C
1
FSELC
Power-On Reset
MR/OE
(All input resistors have a value of 25 k)
0
QC0
QC1
Figure 1. MPC93R52 Logic Diagram
GND
24
V
CC
QB2
QB3
GND
GND
QC0
QC1
V
CC
25
26
27
28
29
30
31
32
1
23
22
21
20
19
18
GND
17
16
15
14
V
CC
QA2
QA1
GND
QA0
V
CC
V
CCA
PLL_EN
13
12
11
10
9
8
FB_IN
QB1
QB0
QA4
6
CCLK
MPC93R52
2
3
4
5
FSELB
F_RANGE
FSELC
FSELA
It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see
Applications Information
section for details
.
Figure 2. Pinout: 32-Lead Package Pinout
(Top View)
MPC93R52 REVISION 5 JANUARY 7, 2013
MR/OE
2
GND
QA3
7
V
CC
V
CC
©2013 Integrated Device Technology, Inc.
MPC93R52 Data Sheet
Table 1. Pin Configuration
Pin
CCLK
FB_IN
F_RANGE
FSELA
FSELB
FSELC
PLL_EN
MR/OE
QA0–4, QB0–3, QC0–1
GND
V
CCA
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Output
Supply
Supply
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
CC
PLL reference clock signal
3.3 V 1:11 LVCMOS Zero Delay Clock Generator
Function
PLL feedback signal input, connect to an output
PLL frequency range select
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
PLL enable/disable
Output enable/disable (high-impedance tristate) and device reset
Clock outputs
Negative power supply
PLL positive power supply (analog power supply). It is recommended to
use an external RC filter for the analog power supply pin V
CCA
. Please
see
Applications Information
section for details.
Positive power supply for I/O and core
V
CC
Supply
V
CC
Table 2. Function Table
Control
Default
0
1
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See
Table 7
and
Table 8
for supported frequency ranges and output to input frequency ratios.
F_RANGE
FSELA
FSELB
FSELC
MR/OE
0
0
0
0
0
VCO
1 (High input frequency range)
Output divider
4
Output divider
4
Output divider
2
Outputs enabled (active)
VCO
2 (Low input frequency range)
Output divider
6
Output divider
2
Output divider
4
Outputs disabled (high-impedance state) and reset of
the device. During reset, the PLL feedback loop is
open and the VCO is operating at its lowest frequency.
The MPC93R52 requires reset after any loss of PLL
lock. Loss of PLL lock may occur when the external
feedback path is interrupted. The length of the reset
pulse should be greater than two reference clock
cycles (CCLK). The device is reset by the internal
power-on reset (POR) circuitry during power-up.
Test mode with PLL disabled. CCLK is substituted for
the internal VCO output. MPC93R52 is fully static and
no minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
PLL_EN
0
Normal operation mode with PLL enabled.
MPC93R52 REVISION 5 JANUARY 7, 2013
3
©2013 Integrated Device Technology, Inc.
MPC93R52 Data Sheet
Table 3. General Specifications
Symbol
V
TT
MM
HBM
LU
C
PD
C
IN
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Power Dissipation Capacitance
Input Capacitance
200
2000
200
10
4.0
Min
Typ
V
CC
2
3.3 V 1:11 LVCMOS Zero Delay Clock Generator
Max
Unit
V
V
V
mA
pF
pF
Condition
Per output
Inputs
Table 4. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.9
V
CC
+ 0.3
V
CC
+ 0.3
20
50
125
Unit
V
V
V
mA
mA
C
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under
absolute-maximum-rated conditions is not implied.
Table 5. DC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0° to 70°C)
Symbol
V
IH
V
IL
V
OH
V
OL
Z
OUT
I
IN
I
CCA
I
CCQ(3)
Characteristics
Input high voltage
Input low voltage
Output High Voltage
Output Low Voltage
2.4
0.55
0.30
14 – 17
200
Min
2.0
Typ
Max
V
CC
+ 0.3
0.8
Unit
V
V
V
V
V
A
V
IN
= V
CC
or
V
IN
= GND
V
CCA
Pin
All V
CC
Pins
Condition
LVCMOS
LVCMOS
I
OH
= –24 mA
(1)
I
OL
= 24 mA
I
OL
= 12 mA
Output impedance
Input Current
(2)
Maximum PLL Supply Current
Maximum Quiescent Supply Current
3.0
7.0
5.0
1.0
mA
mA
1. The MPC93R52 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
series terminated transmission lines.
2. Inputs have pull-down resistors affecting the input current.
3. I
CCQ
is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open.
MPC93R52 REVISION 5 JANUARY 7, 2013
4
©2013 Integrated Device Technology, Inc.
MPC93R52 Data Sheet
Table 6. AC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0° to 70°C)
(1)
Symbol
f
ref
Characteristics
Input reference frequency in PLL mode
(2) (3)
4
feedback
6
feedback
8
feedback
12
feedback
Min
50.0
33.3
25.0
16.67
50.0
200
2
output
(6)
4
output
6
output
8
output
12
output
100
50
33.3
25
16.67
2.0
Typ
3.3 V 1:11 LVCMOS Zero Delay Clock Generator
Max
120.0
80.0
60.0
40.0
250.0
480
240
120
80
60
40
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
Condition
Input reference frequency in PLL bypass mode
(4)
f
VCO
f
MAX
VCO lock frequency range
(5)
Output Frequency
t
PWMIN
t
r
, t
f
t
()
t
sk(O)
Minimum Reference Input Pulse Width
CCLK Input Rise/Fall Time
(7)
Propagation Delay CCLK to FB_IN
(static phase offset)
Output-to-output Skew
(8)
f
ref
> 50 MHz
1.0
–100
+200
150
100
100
50
47
0.1
50
53
1.0
8
10
output frequencies mixed
all outputs same frequency
400
100
450
100
40
50
60
80
2.0 – 8.0
1.0 – 4.0
0.8 – 2.5
0.6 – 1.5
10
ns
ps
ps
ps
ps
ps
%
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
MHz
MHz
MHz
MHz
ms
0.8 to 2.0 V
PLL locked
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
DC
t
r
, t
f
t
PLZ, HZ
t
PZL, LZ
t
JIT(CC)
Output duty cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
0.55 to 2.4 V
t
JIT(PER)
t
JIT()
Period Jitter
I/O Phase Jitter
(9)
output frequencies mixed
all outputs same frequency
4
feedback divider RMS (1
)
6
feedback divider RMS (1
)
8
feedback divider RMS (1
)
12
feedback divider RMS (1
)
4
feedback
6
feedback
8
feedback
12
feedback
BW
PLL closed loop bandwidth
(10)
t
LOCK
1.
2.
3.
4.
5.
6.
7.
Maximum PLL Lock Time
AC characteristics apply for parallel output termination of 50
to V
TT
.
PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation.
The PLL may be unstable with a divide by 2 feedback ratio.
In PLL bypass mode, the MPC93R52 divides the input reference clock.
The input frequency f
ref
on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: f
ref
= f
VCO
FB.
See
Table 7
and
Table 8
for output divider configurations.
The MPC93R52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically t
()
, can only be guaranteed
if t
r
/t
f
are within the specified range.
8. See
Applications Information
section for part-to-part skew calculation.
9. See
Applications Information
section for jitter calculation for other confidence factors with 1
.
10. –3 dB point of PLL transfer characteristics.
MPC93R52 REVISION 5 JANUARY 7, 2013
5
©2013 Integrated Device Technology, Inc.
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