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8532AY-01LF

Description
clock drivers & distribution 17 lvpecl out buffer
Categorysemiconductor    Other integrated circuit (IC)   
File Size247KB,13 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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8532AY-01LF Overview

clock drivers & distribution 17 lvpecl out buffer

8532AY-01LF Parametric

Parameter NameAttribute value
ManufactureIDT (Integrated Device Technology)
Product CategoryClock Drivers & Distributi
RoHSYes
Package / CaseTQFP-52
PackagingTray
Factory Pack Quantity160
Integrated
Circuit
Systems, Inc.
ICS8532AY-01
L
OW
S
KEW
, 1-
TO
-17
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
EATURES
Seventeen differential 3.3V LVPECL outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency: 500MHz
Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 2.5ns (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8532AY-01 is a low skew, 1-to-17, Dif-
ferential-to-3.3V LVPECL Fanout Buffer and a
HiPerClockS™
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8532AY-01 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
IC
S
Guaranteed output and part-to-part skew characteristics make
the ICS8532AY-01 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
CLK
nCLK
PCLK
nPCLK
CLK_SEL
P
IN
A
SSIGNMENT
V
CCO
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
Q0
Q1
Q2
Q3
Q4
Q5
LE
0
1
Q0:Q16
nQ0:nQ16
V
CCO
nc
nc
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
CLK_EN
V
EE
V
CCO
1
2
3
4
5
6
7
8
9
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
34
V
CCO
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
CCO
Q9
nQ9
Q10
nQ10
V
CCO
ICS8532AY-01
33
32
31
30
29
28
10
11
12
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
nQ16
Q16
nQ15
Q15
nQ14
Q14
V
CCO
nQ13
Q13
nQ12
Q12
nQ11
Q11
52-Lead LQFP
10mm x 10mm x 1.4mm body package
Y package
Top View
8532AY-01
www.icst.com/products/hiperclocks.html
1
REV. D
NOVEMBER 04,
2008
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