Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos-
sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is exe-
cuted between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents
TABLE OF CONTENTS ........................................................................................................................................................... 3
LIST OF TABLES .................................................................................................................................................................... 7
LIST OF FIGURES ................................................................................................................................................................... 9
FEATURES ............................................................................................................................................................................ 11
3.2.1 Line Monitor ....................................................................................................................................................................................
3.4 DATA SLICER ..............................................................................................................................................................................................
3.5 CLOCK AND DATA RECOVERY ................................................................................................................................................................
3.7.1 Line Code Rule ...............................................................................................................................................................................
3.7.3 LOS Detection ................................................................................................................................................................................
3.8.1.2 Error Event And Out Of Synchronization Detection ..........................................................................................................
3.8.1.3 Overhead Extraction (T1 Mode SLC-96 Format Only) .....................................................................................................
3.8.2.2 Error Event And Out Of Synchronization Detection ..........................................................................................................
3.8.2.4 V5.2 Link ..........................................................................................................................................................................
ELASTIC STORE BUFFER .......................................................................................................................................................................... 65
RECEIVE PAYLOAD CONTROL ................................................................................................................................................................. 68
RECEIVE SYSTEM INTERFACE ................................................................................................................................................................. 71
3.17.2.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/MRSIGA(MRSIGB) .................................................................................. 78
TRANSMIT SYSTEM INTERFACE .............................................................................................................................................................. 80
TRANSMIT PAYLOAD CONTROL .............................................................................................................................................................. 88
3.20.6 All ‘Zero’s & All ‘One’s ................................................................................................................................................................... 99
3.20.7 Change Of Frame Alignment ......................................................................................................................................................... 99
3.24 WAVEFORM SHAPER / LINE BUILD OUT ...............................................................................................................................................
3.24.2 Line Build Out (LBO) (T1 Only) ...................................................................................................................................................
3.25 LINE DRIVER .............................................................................................................................................................................................
3.27.2.1 System Loopback ...........................................................................................................................................................
3.27.2.3 Local Digital Loopback 1 ................................................................................................................................................
3.27.2.5 Local Digital Loopback 2 ................................................................................................................................................
3.27.2.6 Analog Loopback ............................................................................................................................................................
RECEIVE / TRANSMIT PATH POWER DOWN .........................................................................................................................................
5.1.1.1 Direct Register ................................................................................................................................................................
5.1.2.1 Direct Register ................................................................................................................................................................
5.2.1.1 Direct Register ................................................................................................................................................................
5.2.2.1 Direct Register ................................................................................................................................................................
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) ..................................................................................................................
JTAG DATA REGISTER ............................................................................................................................................................................
TEST ACCESS PORT CONTROLLER ......................................................................................................................................................
5 PROGRAMMING INFORMATION ................................................................................................................................. 119
5.1
5.2
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................................................... 340
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