notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
3/19/2013
1
IS43/46DR86400C, IS43/46DR16320C
GENERAL DESCRIPTION
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue
for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the active
command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A12(x16) or A0-A13(x8)
select the row). The address bits registered coincident with the Read or Write command are used to select the starting
column location A0-A9 for the burst access and to determine if the auto precharge A10 command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command descriptions and device operation.
FUNCTIONAL BLOCK DIAGRAM
DMa - DMb
RDQS,
RDQS
Notes:
1. An:n = no. of address pins - 1
2. DQm: m = no. of data pins - 1
3. For x8 devices:
DMa - DMb = DM; DQSa - DQSb = DQS;
DQSa
-
DQSb
=
DQS;
RDQS,
RDQS
available only for x8
4. For x16 devices:
DMa - DMb = UDM, LDM; DQSa - DQSb = UDQS, LDQS;
DQSa
-
DQSb
=
UDQS, LDQS
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
3/19/2013
IS43/46DR86400C, IS43/46DR16320C
PIN DESCRIPTION TABLE
Symbol
CK,
CK
Type
Input
Function
Clock: CK and
CK
are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of
CK.
Output (read) data is referenced to the crossings of CK and
CK
(both directions of
crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE LOW provides Precharge
Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit, and for self
refresh entry. CKE is asynchronous for self refresh exit. After VREF has become
stable during the power on and initialization sequence, it must be maintained for
proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF
must be maintained to this input. CKE must be maintained HIGH throughout read and
write accesses. Input buffers, excluding CK,
CK,
ODT and CKE are disabled during
power-down. Input buffers, excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when
CS
is registered HIGH.
CS
provides for
external Rank selection on systems with multiple Ranks.
CS
is considered part of the
command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal
to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS,
DQS,
DM
signals. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT.
Command Inputs:
RAS, CAS
and
WE
(along with
CS)
define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. For x8, the function of DM is enabled by EMRS
command to EMR(1) [A11].
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. Bank address also determines if the mode
register or one of the extended mode registers is to be accessed during a MRS or
EMRS command cycle.
Address Inputs: Provide the row address for Active commands and the column
address and Auto Precharge bit for Read/Write commands to select one location
out of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0 -
BA1. The address inputs also provide the op-code during MRS or EMRS commands.
CKE
Input
CS
Input
ODT
RAS, CAS, WE
Input
Input
DM (x8) or
UDM, LDM (x16)
Input
BA0 - BA1
Input
A0 - A13
Input
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
3/19/2013
3
IS43/46DR86400C, IS43/46DR16320C
Symbol
DQ0-7 x8
DQ0-15 x16
Type
Input/
Output
Function
Data Input/Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobes DQS(n) may be used in single ended mode
or paired with optional complementary signals
DQS(n)
to provide differential pair
signaling to the system during both reads and writes. A control bit at EMR(1)[A10]
enables or disables all complementary data strobe signals.
Input/
Output
x8
DQS corresponds to the data on DQ0-DQ7
RDQS corresponds to the Read data on DQ0-DQ7, and is enabled by EMRS
command to EMR(1) [A11].
x16
LDQS corresponds to the data on DQ0-DQ7
UDQS corresponds to the data on DQ8-DQ15
NC
VDDQ
VSSQ
VDDL
VSSDL
VDD
VSS
VREF
Supply
Supply
Supply
Supply
Supply
Supply
Supply
No Connect: No internal electrical connection is present.
DQ Power Supply: 1.8 V +/- 0.1 V
DQ Ground
DLL Power Supply: 1.8 V +/- 0.1 V
DLL Ground
Power Supply: 1.8 V +/- 0.1 V
Ground
Reference voltage
DQS, (DQS)
RDQS, (RDQS) x8
UDQS, (UDQS),
LDQS, (LDQS) x16
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
3/19/2013
IS43/46DR86400C, IS43/46DR16320C
PIN CONFIGURATION
PACKAGE CODE: B 60 BALL FBGA (Top View) (8.00 mm x 10.5 mm Body, 0.8 mm Ball Pitch)
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