4Gb DDR3L
-
AS4C512M8D3L
512M x 8 bit DDR3L Synchronous DRAM (SDRAM)
Confidential
Features
JEDEC Standard Compliant
Power supplies: V
DD
& V
DDQ
= +1.35V
Backward compatible to V
DD
& V
DDQ
= 1.5V ±0.075V
Operating temperature:
- Commercial (Extended) (0 ~ 95°C)
- Industrial (-40 ~ 95°C)
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 800MHz
Differential Clock, CK & CK#
Bidirectional differential data strobe
- DQS & DQS#
8 internal banks for concurrent operation
8n-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Additive Latency (AL): 0, CL-1, CL-2
Programmable Burst lengths: 4, 8
Burst type: Sequential / Interleave
Output Driver Impedance Control
8192 refresh cycles / 64ms
- Average refresh period
7.8μs @ -40℃
≦TC≦
+85℃
3.9μs @ +85℃
＜TC≦
+95℃
Write Leveling
OCD Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
RoHS compliant
Auto Refresh and Self Refresh
78-ball 9 x 10.5 x 1.2mm FBGA package
-
All parts are ROHS Compliant
Advanced (Rev. 2.0, Aug. /2014)
Overview
The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is
double data rate architecture to achieve high-speed
operation. It is internally configured as an eight bank
DRAM.
The 4Gb chip is organized as 64Mbit x 8 I/Os x 8 bank
devices. These synchronous devices achieve high
speed double-data-rate transfer rates of up to 1600
Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3L
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the
cross point of differential clocks (CK rising and CK#
falling). All I/Os are synchronized with differential DQS
pair in a source synchronous fashion.
These devices operate with a single 1.35V -0.067V
/+0.1V power supply and are available in BGA
packages.
Table 1. Speed Grade Information
Speed Grade
DDR3L-1600
Clock Frequency
800 MHz
CAS Latency
11
t
RCD
(ns)
13.75
t
RP
(ns)
13.75
Table 2. Ordering Information
Product part No
AS4C512M8D3L-12BCN
AS4C512M8D3L-12BIN
Org
512M x 8
512M x 8
Temperature
Commercial (Extended)
0°C to 95°C
Industrial
-40°C to 95°C (Extended)
Package
78-ball FBGA
78-ball FBGA
Confidential
2
Rev. 2.0
Aug. /2014
4Gb DDR3L
-
AS4C512M8D3L
Figure 3. State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands
to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination,
and some other events are not captured in full detail.
Power
applied
Power
On
Reset
Procedure
Initialization
MRS,MPR,
Write
Leveling
E
Self
Refresh
from any
RESET
state
ZQ
Calibration
ZQCL,ZQCS
Idle
SR
ZQCL
MRS
SR
X
REF
Refreshing
PD
ACT
E
PD
X
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Write = WR, WRS4, WRS8
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
Active
Power
Down
PD
X
PD
E
Activating
Precharge
Power
Down
Bank
Activating
RE
AD
TE
RI
W
WR
ITE
A
WRITE
READ
Writing
READ
WRITE
DA
EA
R
Reading
WRITE A
READ A
EA
RIT
W
PRE, PREA
RE
AD
A
PR
Writing
EA
PR
E,
PR
Reading
E
,P
RE
A
Automatic Sequence
Command Sequence
Precharging
Confidential
5
Rev. 2.0
Aug. /2014
Real-time operating system RTOS
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