23A512/23LC512
512Kbit SPI Serial SRAM with SDI and SQI Interface
Device Selection Table
Part
Number
23A512
23LC512
Note 1:
V
CC
Range
1.7-2.2V
2.5-5.5V
16 MHz for E-temp.
Temp.
Ranges
I, E
I, E
Dual I/O
(SDI)
Yes
Yes
Quad I/O
(SQI)
Yes
Yes
Max. Clock
Frequency
20 MHz
(1)
20 MHz
(1)
Packages
SN, ST, P
SN, ST, P
Features:
• SPI-Compatible Bus Interface:
- 20 MHz Clock rate
- SPI/SDI/SQI mode
• Low-Power CMOS Technology:
- Read Current: 3 mA at 5.5V, 20 MHz
- Standby Current: 4
A
at +85°C
• Unlimited Read and Write Cycles
• Zero Write Time
• 64K x 8-bit Organization:
- 32-byte page
• Byte, Page and Sequential mode for Reads and
Writes
• High Reliability
• Temperature Ranges Supported:
- Industrial (I):
-40C to +85C
- Automotive (E):
-40C to +125C
• RoHS Compliant
• 8-Lead SOIC, TSSOP and PDIP Packages
Description:
The Microchip Technology Inc. 23A512/23LC512 are
512Kbit Serial SRAM devices. The memory is
accessed via a simple Serial Peripheral Interface (SPI)
compatible serial bus. The bus signals required are a
clock input (SCK) plus separate data in (SI) and data
out (SO) lines. Access to the device is controlled
through a Chip Select (CS) input. Additionally, SDI
(Serial Dual Interface) and SQI (Serial Quad Interface)
is supported if your application needs faster data rates.
This device also supports unlimited reads and writes to
the memory array.
The 23A512/23LC512 is available in standard
packages including 8-lead SOIC, PDIP and advanced
8-lead TSSOP.
Package Types (not to scale)
SOIC/TSSOP/PDIP
Pin Function Table
Name
CS
SO/SIO1
SIO2
V
SS
SI/SIO0
SCK
HOLD/SIO3
V
CC
Function
Chip Select Input
Serial Output/SDI/SQI Pin
SQI Pin
Ground
Serial Input/SDI/SQI Pin
Serial Clock
Hold/SQI Pin
Power Supply
CS
SO/SIO1
SIO2
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD/SIO3
SCK
SI/SIO0
2012-2013 Microchip Technology Inc.
DS20005155B-page 1
23A512/23LC512
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+0.3V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias .............................................................................................................-40°C to +125°C
†
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C
Automotive (E): T
A
= -40°C to +125°C
Min.
1.7
2.5
0.7 V
CC
-0.3
—
V
CC
- 0.5
—
—
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
1
3
1
—
4
—
—
1.0
Max.
2.2
5.5
V
CC
+ 0.3
0.2 V
CC
0.1 V
CC
0.2
—
±1
±1
10
10
4
12
10
20
7
—
Units
V
V
V
V
V
A
A
mA
mA
A
A
A
A
pF
V
Test Conditions
23A512
23LC512
—
23A512
23LC512
I
OL
= 1 mA
I
OH
= -400
A
CS = V
CC
, V
IN
= V
SS OR
V
CC
CS = V
CC
, V
OUT
= V
SS OR
V
CC
F
CLK
= 20 MHz; SO = O, 2.2V
F
CLK
= 20 MHz; SO = O, 5.5V
CS = V
CC
= 2.2V, Inputs tied to
V
CC
or V
SS
, I-Temp
CS = V
CC
= 2.2V, Inputs tied to
V
CC
or V
SS
, E-Temp
CS = V
CC
= 5.5V, Inputs tied to
V
CC
or V
SS
, I-Temp
CS = V
CC
= 5.5V, Inputs tied to
V
CC
or V
SS
, E-Temp
V
CC
= 5.0V, f = 1 MHz, T
A
= 25°C
(Note
1)
(Note
2)
DC CHARACTERISTICS
Param.
No.
D001
D002
D003
D004
D005
D006
D007
D008
D009
Sym.
V
CC
V
IH
V
IL
V
OL
V
OH
I
LI
I
LO
Characteristic
Supply voltage
High-level input
voltage
Low-level input
voltage
Low-level output
voltage
High-level output
voltage
Input leakage
current
Output leakage
current
I
CC
Read Operating current
I
CCS
Standby current
D010
D011
Note 1:
2:
3:
C
INT
V
DR
Input capacitance
RAM data retention
voltage
—
—
This parameter is periodically sampled and not 100% tested.
This is the limit to which V
CC
can be lowered without losing RAM data. This parameter is periodically
sampled and not 100% tested.
Typical measurements taken at room temperature.
DS20005155B-page 2
2012-2013 Microchip Technology Inc.
23A512/23LC512
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
The 23A512/23LC512 is an 512Kbit Serial SRAM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC
®
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol. In addition, the 23A512/
23LC512 is also capable of operating in SDI/SQI high
speed SPI mode.
The 23A512/23LC512 contains an 8-bit instruction reg-
ister. The device is accessed via the SI pin, with data
being clocked in on the rising edge of SCK. The CS pin
must be low for the entire operation.
Table 2-1
contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
If operating in Sequential mode, the data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
Address Pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached (FFFFh),
the address counter rolls over to address 0000h,
allowing the read cycle to be continued indefinitely.
The read operation is terminated by raising the CS
pin.
2.4
Write Sequence
Prior to any attempt to write data to the 23A512/
23LC512, the device must be selected by bringing CS
low.
Once the device is selected, the Write command can
be started by issuing a
WRITE
instruction, followed by
the 16-bit address, and then the data to be written. A
write is terminated by the CS being brought high.
If operating in Page mode, after the initial data byte is
shifted in, additional bytes can be shifted into the
device. The Address Pointer is automatically
incremented. This operation can continue for the entire
page (32 bytes) before data will start to be overwritten.
If operating in Sequential mode, after the initial data
byte is shifted in, additional bytes can be clocked into
the device. The internal Address Pointer is automati-
cally incremented. When the Address Pointer reaches
the highest address (FFFFh), the address counter rolls
over to (0000h). This allows the operation to continue
indefinitely, however, previous data will be overwritten.
2.2
Modes of Operation
The 23x512 has three modes of operation that are
selected by setting bits 7 and 6 in the MODE register.
The modes of operation are Byte, Page and Burst.
Byte Operation
– is selected when bits 7 and 6 in the
MODE register are set to
00.
In this mode, the read/
write operations are limited to only one byte. The
Command followed by the 16-bit address is clocked into
the device and the data to/from the device is transferred
on the next eight clocks (Figure
2-1, Figure 2-2).
Page Operation
– is selected when bits 7 and 6 in the
MODE register are set to
10.
The 23x512 has 2048
pages of 32 bytes. In this mode, the read and write oper-
ations are limited to within the addressed page (the
address is automatically incremented internally). If the
data being read or written reaches the page boundary,
then the internal address counter will increment to the
start of the page (Figure
2-3, Figure 2-4).
Sequential Operation
– is selected when bits 7 and 6
in the MODE register are set to
01.
Sequential opera-
tion allows the entire array to be written to and read
from. The internal address counter is automatically
incremented and page boundaries are ignored. When
the internal address counter reaches the end of the
array, the address counter will roll over to
0x0000
(Figure
2-5, Figure 2-6).
2.3
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ
instruction is transmitted to the 23A512/23LC512
followed by the 16-bit address. After the correct
READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin.
2012-2013 Microchip Technology Inc.
DS20005155B-page 5
FPGA/CPLD
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