AS4C8M32S
Revision History AS4C8M32S- 90 Ball TFBGA PACKAGE
Revision
Rev 1.0
Rev 1.1
Rev 2.0
Details
Preliminary datasheet
Added 166MHz option -6 clock cycle time
Typing error page 1 – fast clock rate error
133MHz should be 143MHz
Typing error - Frequency in Table 2. Ordering information
7-BCN reflected as 133MHz – changed to 143MHz
Date
February 2013
February 2013
May 2014
May 2014
Alliance Memory Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc.
reserves the right to change products or specification without notice.
AS4C8M32S
8M x 32 bit Synchronous DRAM (SDRAM)
Confidential
Features
Fast access time from clock: 5/5.4 ns
Fast clock rate: 166/143MHz
Fully synchronous operation
Internal pipelined architecture
2M word x 32-bit x 4-bank
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential & interleaved
- Burst stop function
Auto Refresh and Self Refresh
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V power supply
Interface: LVTTL
90-ball, 8.0 x 13 x 1.4mm TFBGA package
- Pb and Halogen Free
Advanced (Rev.
2.0 May
/2014)
Overview
The
256Mb AS4C8M32S SDRAM
is a high-
speed CMOS synchronous DRAM containing 256
Mbits. It is internally configured as 4 Banks of 2M
word x 32 DRAM with a synchronous interface (all
signals are registered on the positive edge of the
clock signal, CLK). Read and write accesses to the
SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed
number of locations in a programmed sequence.
Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
The SDRAM provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with
a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications
Table 1. Key Specifications
AS4C8M32S
tCK3
Clock Cycle time(min.)
tAC3
tRAS
tRC
Access time from CLK (max.)
Row Active time(min.)
Row Cycle time(min.)
-6/7
6/7.5 ns
5/5.4 ns
42/45 ns
60/67.5 ns
Table 2.Ordering Information
Part Number
AS4C8M32S-6BIN
AS4C8M32S-7BCN
Frequency
166MHz
143MHz
Package
90-ball TFBGA
90-ball TFBGA
Temperature
Industrial
Commercial
Temp Range
-40 ~ 85°C
0 ~ 70°C
B: indicates 90-ball (8.0 x 13 x 1.4mm) TFBGA package
N: indicates Pb and Halogen Free ROHS
Alliance Memory, Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800
FAX: (650) 620-9211
Alliance Memory, Inc. reserves the right to change products or specification without notice.
AS4C8M32S
Figure 1. Ball Assignment (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26
DQ28
.
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQM1
VDDQ
VSSQ
VSSQ
DQ11
DQ13
2
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
VDDQ
DQ15
3
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
…
7
VDD
VDDQ
.
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS#
VDD
DQ6
DQ1
VDDQ
VDD
8
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS#
WE#
DQ7
DQ5
DQ3
VSSQ
DQ0
9
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
RAS#
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
Alliance Memory Confidential
2
Rev.
2.0
May
/2014
AS4C8M32S
Figure 2. Block Diagram
CKE
Row
Decoder
CLK
CLOCK
BUFFER
2M x 32
CELL ARRAY
(BANK #A)
Column Decoder
CS#
RAS#
CAS#
WE#
DQ31
DQM0 ~ DQM3
Row
Decoder
A10/AP
COLUMN
COUNTER
MODE
REGISTER
2M x 32
CELL ARRAY
(BANK #B)
Column Decoder
A0
A9
A11
BA0
BA1
~
ADDRESS
BUFFER
REFRESH
COUNTER
Row
Decoder
2M x 32
CELL ARRAY
(BANK #C)
Column Decoder
Row
Decoder
2M x 32
CELL ARRAY
(BANK #D)
Column Decoder
Alliance Memory Confidential
3
Rev. 2.0 May /2014
~
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
DQ
Buffer
DQ0
AS4C8M32S
Pin Descriptions
Table 1. Pin Details
Symbol Type Description
CLK
Input
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the
output registers.
Input
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes
low synchronously with clock (set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. When all banks are in the idle state, deactivating the clock
controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except
after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes, providing low standby power.
Input
Bank Activate:
BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. The bank address BA0 and BA1 is used latched
in mode register set.
CKE
BA0,
BA1
A0-A11 Input
Address Inputs:
A0-A11 are sampled during the BankActivate command (row address A0-
A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge)
to select one location out of the 2M available in the respective bank. During a Precharge
command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH).
The address inputs also provide the op-code during a Mode Register Set or Special Mode
Register Set command.
CS#
Input
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
Input
Row Address Strobe:
The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate
command or the Precharge command is selected by the WE# signal. When the WE# is
asserted "HIGH," the BankActivate command is selected and the bank designated by BA is
turned on to the active state. When the WE# is asserted "LOW," the Precharge command is
selected and the bank designated by BA is switched to the idle state after the precharge
operation.
Input
Column Address Strobe:
The CAS# signal
conjunction with the RAS# and WE# signals and
When RAS# is held "HIGH" and CS# is asserted
asserting CAS# "LOW." Then, the Read or Write
"LOW" or "HIGH."
defines the operation commands in
is latched at the positive edges of CLK.
"LOW," the column access is started by
command is selected by asserting WE#
RAS#
CAS#
WE#
Input
Write Enable:
The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used
to select the BankActivate or Precharge command and Read or Write command.
DQM0 - Input
Data Input/Output Mask: Data Input Mask:
DQM0-DQM3 are byte specific. Input data is
DQM3
masked when DQM is sampled HIGH during a write cycle. DQM3 masks DQ31-DQ24,
DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
DQ0- Input/
Data I/O:
The DQ0-31 input and output data are synchronized with the positive edges of
DQ31 Output CLK. The I/Os are byte-maskable during Reads and Writes.
NC
V
DDQ
V
SSQ
-
No Connect:
These pins should be left unconnected.
Supply
DQ Power:
Provide isolated power to DQs for improved noise immunity.
Supply
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
Alliance Memory Confidential
4
Rev. 2.0 May /2014
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