AS4C32M16MD1
512M (32M x16 bit) Mobile DDR SDRAM
Confidential
(Rev. 2.0, Feb. /2014)
1. FEATURES
•
Density :
512Mbit
•
Organization
- x16 bit : 8M words x 16bits x 4banks
•
Power supply :
VDD, VDDQ = 1.7 to 1.95V
•
Speed
- Clock frequency : 200MHz (max.)
- Data rate : 400Mbps (max.)
•
2KB page size
- Row address : A0 to A12
- Column address : A0 to A9 (x16 bits)
•
Four internal banks for concurrent
operation
•
Interface :
LVCMOS
•
Burst lengths (BL)
: 2, 4, 8, 16
•
Burst type (BT)
- Sequential : 2, 4, 8, 16
- Interleave : 2, 4, 8, 16
•
CAS# latency (CL)
: 3
•
Precharge :
auto precharge option for each
burst access
•
Driver strength :
normal, 1/2, 1/4, 1/8
•
Refresh :
auto-refresh, self-refresh
•
Refresh cycles :
8192 cycles/64ms
- Average refresh period : 7.8us
•
Operating junction temperature range
- Tj= -30℃ to +85℃
Package:
60-ball FBGA (8x9mm)
All parts are ROHS Compliant
•
Low power consumption
•
Partial Array Self-Refresh (PASR)
•
Auto Temperature Compensated Self-Refresh
(ATCSR) by built-in temperature sensor
•
Deep power down mode
•
Burst termination by burst stop command and
precharge command
•
DDL is not implemented
•
Double-data-rate architecture :
Two data transfers per one clock cycle
•
The high speed data transfer is realized by the
2bits prefetch pipelined architecture
•
Bi-directional data strobe (DQS) is transmitted/
received with data for capturing data at the
receiver
•
DQS is edge-aligned with data for READs;
center-aligned with data for WRITEs
•
Differential clock inputs (CK and CK#)
•
Commands entered on each positive CK edge;
data and data mask referenced to both edges
of DQS
•
Data mask (DM) for write data
Confidential
3
Rev. 2.0/February 2014
AS4C32M16MD1
2. GENERAL DESCRIPTION
This device is 536,870,912 bits of double data rate synchronous DRAM organized as 4 banks of
8,388,608 words by 16 bits. The synchronous operation with Data Strobe allows extremely high
performance.
J
SC is applied to reduce leakage and refresh currents while achieving very high speed.
I/O transactions are possible on both edges of the clock. The ranges of operating frequencies,
programmable burst length and programmable latencies allow the device to be useful for a variety of
high performance memory system applications.
Table 1. Speed Grade Information
Speed Grade – Data rate Clock Frequency
400Mbps (max)
200 MHz (max)
CAS Latency
3
t
RCD
(ns)
15
t
RP
(ns)
15
Table 2
–
Ordering Information for ROHS Compliant Products
Product part No
AS4C32M16MD1-5BCN
Org
32 x 16
Temperature
-30°C
to
85°C
Max Clock (MHz)
200
Package
60-ball FBGA
Confidential
4
Rev. 2.0/February 2014
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