Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
G
ENERAL
D
ESCRIPTION
The 87604I is a 1:4 PCI/PCI-X Clock Generator. The 87604I has
a selectable REF_IN or crystal input. The REF_IN input accepts
LVCMOS or LVTTL input levels. The 87604I has a fully integrated
PLL along with frequency configurable clock and feedback outputs
for multiply-ing and regenerating clocks with “zero delay”. The
PLL’s VCO has an operating range of 250MHz - 500MHz, allowing
this device to be used in a variety of general purpose clocking
applications. For PCI/PCI-X applications in particular, the VCO
frequency should be set to 400MHz. This can be accomplished
by supplying 33.33MHz, 25MHz, 20MHz, or 16.66MHz on the
reference clock or crystal input and by selecting ÷12, ÷16, ÷20, or
÷24, respectively as the feedback divide value. The divider on the
output bank can then be configured to generate 33.33MHz (÷12),
66.66MHz (÷6), 100MHz (÷4), or 133.33MHz (÷3).
The 87604I is character ized to operate with its core
supply at 3.3V and the bank supply at 3.3V or 2.5V. The
87604I is packaged in a small 6.1mm x 9.7mm TSSOP
body, making it ideal for use in space-constrained applications.
87604I
DATA SHEET
F
EATURES
•
Fully integrated PLL
•
Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
•
Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_IN clock input
•
Maximum output frequency: 166.67MHz
•
Maximum crystal input frequency: 38MHz
•
Maximum REF_IN input frequency: 41.67MHz
•
Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz
•
Separate feedback control for generating PCI / PCI-X
frequencies from a 16.66MHz or 20MHz crystal, or 25MHz
or 33.33MHz reference frequency
•
VCO range: 250MHz to 500MHz
•
Cycle-to-cycle jitter: 120ps (maximum)
•
Period jitter, RMS: 20ps (maximum)
•
Output skew: 65ps (maximum)
•
Static phase offset: 160ps ± 160ps
•
Voltage Supply Modes:
V
DD
/V
DDA
/V
DDO
3.3/3.3/3.3
3.3/3.3/2.5
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
DD
FB_IN
GND
FB_OUT
REF_OUT
V
DDO
Q3
Q2
GND
Q1
Q0
V
DDO
PLL_SEL
V
DDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FBDIV_SEL1
FBDIV_SEL0
DIV_SEL1
DIV_SEL0
nc
MR
nc
GND
GND
nc
REF_IN
XTAL_OUT
XTAL_IN
XTAL_SEL
87604I
28-Lead TSSOP, 240MIL
6.1mm x 9.7mm x 0.92mm
body package
G Package
Top View
87604I REVISION B 11/11/15
1
©2015 Integrated Device Technology, Inc.
87604I DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 9, 20, 21
4
5
6, 12
7, 8,
10, 11
13
14
15
16,
17
18
19, 22, 24
23
25,
26
27,
28
Name
V
DD
FB_IN
GND
FB_OUT
REF_OUT
V
DDO
Q3, Q2,
Q1, Q0
PLL_SEL
V
DDA
XTAL_SEL
XTAL_IN,
XTAL_OUT
REF_IN
nc
MR
DIV_SEL0,
DIV_SEL1
FBDIV_SEL0,
FBDIV_SEL1
Power
Input
Power
Output
Output
Power
Output
Input
Power
Input
Input
Input
Unused
Input
Input
Input
Pullup
Pullup
Pulldown
Type
Description
Core supply pin.
Feedback input to phase detector for generating clocks with
“zero delay”. LVCMOS / LVTTL interface levels.
Power supply ground.
Feedback output. Connect to FB_IN. LVCMOS / LVTTL interface levels.
Reference clock output. LVCMOS / LVTTL interface levels.
Output supply pin
Clock outputs. 15
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
Analog supply pin. See Applications Note for filtering.
Selects between crystal oscillator or reference clock as the PLL reference
source. Selects XTAL inputs when HIGH. Selects REF_IN when LOW.
LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
No connect.
Active HIGH Master Reset. When logic HIGH, the internal dividers
Pulldown are reset causing the outputs go low. When logic LOW, the internal divid-
ers and the outputs are enabled. LVCMOS / LVTTL interface levels.
Selects divide value for clock outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Selects divide value for reference clock output and feedback output.
Pulldown
LVCMOS / LVTTL interface levels.
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output); NOTE 1
Output Impedance
V
DD
, V
DDA
, V
DDO
= 3.465V
V
DD
, V
DDA
= 3.465V; V
DDO
= 2.625V
15
Test Conditions
Minimum
Typical
4
51
51
9
11
Maximum
Units
pF
kΩ
kΩ
pF
pF
Ω
Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
2
REVISION B 11/11/15
87604I DATA SHEET
T
ABLE
3A. O
UTPUT
C
ONTROL
P
IN
F
UNCTION
T
ABLE
Inputs
MR
1
0
Q0:Q3
LOW
Active
Outputs
FB_OUT, REF_OUT
LOW
Active
T
ABLE
3B. O
PERATING
M
ODE
F
UNCTION
T
ABLE
Inputs
PLL_SEL
0
1
Operating Mode
Bypass
PLL
T
ABLE
3C. PLL I
NPUT
F
UNCTION
T
ABLE
Inputs
XTAL_SEL
0
1
PLL Input
REF_IN
XTAL Oscillator
T
ABLE
3D. C
ONTROL
F
UNCTION
T
ABLE
Inputs
Reference
Frequency
Range (MHz)
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
10 - 25
10 - 25
10 - 25
10 - 25
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
Outputs
PLL_SEL=1
DIV_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q0:Q3
x4
x3
x2
x1
x 5.33
x4
x 2.667
x 1.33
x 6.667
x5
x 3.33
x 1.66
x8
x6
x4
x2
Frequency
Q0:Q3 (MHz)
66.68 - 166.68
50 - 125
33.34 - 83.34
16.67 - 41.67
66.63 - 166.56
50 - 125
33.34 - 83.34
16.63 - 41.56
66.67 - 166.68
50 - 125
33.30 - 83.25
16.60 - 41.50
66.64 - 166.64
50 - 125
33.32 - 83.32
16.66 - 41.66
FB_OUT
(MHz)
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
10 - 25
10 - 25
10 - 25
10 - 25
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
FBDIV_SEL1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FBDIV_SEL0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DIV_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
NOTE: VCO frequency range for all configurations above is 250MHz to 500MHz.
REVISION B 11/11/15
3
Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
87604I DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
64.5°C/W (0 mps)
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
185
15
20
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
Input
High Voltage
MR, DIV_ SEL0, DIV_SEL1,
FBDIV_SEL0, FBDIV_SEL1,
XTAL_SEL, FB_IN, PLL_SEL
REF_IN
Input
Low Voltage
MR, DIV_ SEL0, DIV_SEL1,
FBDIV_SEL0, FBDIV_SEL1,
XTAL_SEL, FB_IN, PLL_SEL
REF_IN
Input
High Current
DIV_ SEL0, DIV_SEL1, FB-
DIV_SEL0, FBDIV_SEL1, MR,
FB_IN
XTAL_SEL, PLL_SEL
DIV_ SEL0, DIV_SEL1, FB-
DIV_SEL0, FBDIV_SEL1, MR,
FB_IN
XTAL_SEL, PLL_SEL
VIN = 0V
VDD = 3.465V,
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V + 0.3
DD
Units
V
V
V
V
µA
µA
µA
V
IH
V + 0.3
DD
V
IL
0.8
1.3
150
5
I
IH
V =V = 3.465V
DD
IN
V =V = 3.465V
DD
IN
-5
VIN = 0V
VDD = 3.465V,
I
IL
Input
Low Current
-150
V =V = 3.465V
DD
IN
µA
V
V
0.5
V
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.6
1.8
V =V = 2.625V
DD
IN
DD
IN
V =V = 3.465V or
2.625V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement Information section,
“3.3V Output Load Test Circuit”.
Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
4
REVISION B 11/11/15
87604I DATA SHEET
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
7
1
10
Test Conditions
Minimum
Typical Maximum
38
50
Units
MHz
Ω
pF
mW
Fundamental
T
ABLE
6. PLL I
NPUT
R
EFERENCE
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
REF
Parameter
Reference Frequency
Test Conditions
Minimum
8.33
Typical
Maximum
41.67
Units
MHz
T
ABLE
7A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t(Ø)
tsk(o)
tjit(cc)
tjit(per)
tsl(o)
t
L
t
R
/ t
F
Parameter
Output Frequency
Static Phase Offset; NOTE 1
Output Skew; NOTE 2, 5
Cycle-to-Cycle Jitter; 5
Period Jitter, RMS; NOTE 3, 5, 6
Slew Rate
PLL Lock Time
Output Rise/Fall Time
20% to 80%
200
1
FREF = 25MHz
0
160
Test Conditions
Minimum
Typical
Maximum
166.67
325
65
120
20
4
10
700
Units
MHz
ps
ps
ps
ps
V/ns
ms
ps
odc
Output Duty Cycle; NOTE 4
48
52
%
NOTE: All parameters measured with feedback and output dividers set to DIV by 12 unless otherwise noted.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the
PLL is locked and the input reference frequency is stable. Measured at V
DD
/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Jitter performance using LVCMOS inputs.
NOTE 4: Measured using REF_IN. For XTAL input, refer to Application Note.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: This parameter is defined as an RMS value.
T
ABLE
7B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t(Ø)
tsk(o)
tjit(cc)
tjit(per)
tsl(o)
t
L
t
R
/ t
F
odc
Parameter
Output Frequency
Static Phase Offset; NOTE 1
Output Skew; NOTE 2, 5
Cycle-to-Cycle Jitter; 5
Period Jitter, RMS; NOTE 3, 5, 6
Slew Rate
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle; NOTE 4
20% to 80%
200
48
1
FREF = 25MHz
-365
-105
Test Conditions
Minimum
Typical
Maximum
166.67
160
50
170
20
4
10
700
52
Units
MHz
ps
ps
ps
ps
V/ns
ms
ps
%
See Table 7A for notes.
REVISION B 11/11/15
5
Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
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