Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -55NC to +125NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
Supply Voltage
I
2
C Voltage (Note 2)
SYMBOL
V
CC
1.8V
V
CI2C
3.3V
5V
Supply Current
Power-On-Reset Trip Point
IO PIN: GENERAL DATA
1-Wire Input High Voltage
1-Wire Input Low Voltage
1-Wire Weak Pullup Resistor
1-Wire Output Low Voltage
Active Pullup On-Threshold
Active Pullup On-Time (Note 3)
V
IH1
V
IL1
R
WPU
V
OL1
V
IAPO
t
APU
V
CC
= full range
V
CC
= full range
Low range
High range
I
OL
= 8mA sink current
V
CC
= full range
1-Wire time slot
1-Wire reset standard speed
1-Wire reset overdrive speed
Active Pullup Impedance
1-Wire Output Fall Time (Note 4)
IO PIN: 1-Wire TIMING (Note 5)
Reset Low Time
Reset High Time
t
RSTL
t
RSTH
Standard
Overdrive
Standard and overdrive
-5%
See
Table 7
+5%
Fs
Fs
R
APU
t
F1
V
CC
= 3.0V, 4mA load
V
CC
= 4.5V, 4mA load
Standard, 10pF < C
LOAD
< 400pF
Overdrive, 10pF < C
LOAD
< 400pF
0.25
0.05
0.6
2.375
0.475
0.95
2.5
0.5
375
700
500
1000
0.6
O
V
CC
0.2
O
V
CC
815
1375
0.2
1.2
2.625
0.525
60
40
1
0.2
I
Fs
See APU bit description
Fs
V
V
I
V
V
I
CC
V
POR
No communication, V
CC
= full range
Sleep mode, V
CC
= 5.25V
Sleep mode, V
CC
= 3.6V
V
CC
= full range
1.0
CONDITIONS
MIN
2.97
1.71
2.97
4.5
1.8
3.3
5.0
TYP
MAX
5.25
1.89
3.63
5.25
300
4
3.0
1.5
V
FA
V
UNITS
V
Equal to t
RSTL
Maxim Integrated
2
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
Presence-Detect Sample Time
Sampling for Short and Interrupt
Write-One/Read Low Time
Read Sample Time
Write-Zero Low Time
Write-Zero Recovery Time
1-Wire Time Slot
SLPZ PIN
Low-Level Input Voltage
High-Level Input Voltage
Input Leakage Current (Note 2)
Wake-Up Time from Sleep Mode
I
2
C SCL AND SDA PINS (Note 9)
Low-Level Input Voltage
High-Level Input Voltage
V
IL
V
IH
V
CI2C
> 2.0V
V
HYS
V
CI2C
< 2.0V
V
CI2C
> 2.0V
V
OL
V
CI2C
< 2.0V
(Note 4)
60
V
CI2C
= full range
-0.5
0.7
O
V
CI2C
0.05
O
V
CI2C
0.1
O
V
CI2C
0.4
0.2
O
V
CI2C
250
50
V
0.3
O
V
CI2C
V
CI2C
+
0.5V
V
V
V
IL
V
IH
I
I
t
SWUP
V
CC
= full range
(Note 7)
V
CI2C
< 1.89V
V
CI2C
< 3.63V
V
CI2C
< 5.25V
(Notes 4, 8)
-0.5
1.3
+0.5
V
CCACT
6
15
32
2
ms
FA
V
V
SYMBOL
t
MSP
t
SI
t
W1L
t
MSR
t
W0L
t
REC0
t
SLOT
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive (Note 6)
Standard
Overdrive
Standard
Overdrive
Standard and overdrive
Standard and overdrive
CONDITIONS
MIN
-5%
7.6
0.71
7.6
0.71
11.4
1.66
-5%
-5%
TYP
See
Table 7
8
0.75
8
0.75
12
1.75
See
Table 7
See
Table 7
MAX
+5%
8.4
0.79
8.4
0.79
12.6
1.84
+5%
+5%
UNITS
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Equal to t
W0L
+ t
REC0
Hysteresis of Schmitt Trigger
Inputs (Note 4)
V
Low-Level Output Voltage at
3mA Sink Current
Output Fall Time from V
IH(MIN)
to
V
IL(MAX)
with a Bus Capacitance
from 10pF to 400pF
Pulse Width of Spikes
Suppressed by Input Filter
t
OF
t
SP
ns
ns
Maxim Integrated
3
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
Input Current with Input Voltage
Between 0.1
O
V
CC(MAX)
and 0.9
O
V
CC(MAX)
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition (After this period, the
first clock pulse is generated.)
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP
and START Condition
Capacitive Load for Each Bus
Line
Oscillator Warmup Time
SYMBOL
I
I
C
I
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
BUF
C
B
t
OSCWUP
(Notes 4, 14)
(Notes 4, 8)
(Notes 11, 12)
(Note 13)
250
0.6
1.3
400
2
(Note 10)
(Note 4)
0
0.6
1.3
0.6
0.6
0.9
CONDITIONS
MIN
-10
TYP
MAX
+10
10
400
UNITS
FA
pF
kHz
Fs
Fs
Fs
Fs
Fs
ns
Fs
Fs
pF
ms
Note 1:
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2:
The V
CI2C
voltage is applied at the SLPZ pin. V
CI2C
must always be < V
CC
. The DS2483 measures V
CI2C
after t
SWUP
(wakeup from sleep mode) or after t
OSCWUP
(power-on reset). The
Device Reset
command does not cause the DS2483 to
measure V
CI2C
.
Note 3:
The active pullup does not apply to the rising edge of a presence pulse outside of a
1-Wire Reset
command or during the
recovery after a short on the 1-Wire line.
Note 4:
Guaranteed design and not production tested.
Note 5:
Except for t
F1
, all 1-Wire timing specifications are derived from the same timing circuit.
Note 6:
Although 1-Wire slave data sheets specify a t
W1L
and t
RL
minimum of 1µs, 1-Wire slaves will accept the shorter 0.71µs
t
W1L
and t
RL
of the DS2483.
Note 7:
V
CCACT
refers to the V
CC
level being applied in the application.
Note 8:
I
2
C communication should not take place for the max t
OSCWUP
or t
SWUP
time following a power-on reset or a wake-up
from sleep mode.
Note 9:
All I
2
C timing values are referenced to V
IH(MIN)
and V
IL(MAX)
levels.
Note 10:
The DS2483 does not obstruct the SDA and SCL lines if SLPZ is at 0V or if V
CC
is switched off.
Note 11:
The DS2483 provides a hold time of at least 300ns for the SDA signal (referenced to the V
IH(MIN)
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12:
The maximum t
HD:DAT
must only be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
Note 13:
A fast mode I
2
C bus device can be used in a standard mode I
2
C bus system, but the requirement t
SU:DAT
R
250ns
must then be met. This requirement is met since the DS2483 does not stretch the low period of the SCL signal. Also the
acknowledge timing must meet this setup time (I
2
C bus specification Rev. 03, 19 June 2007).
Note 14:
C
B
= Total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depend-
ing on the actual operating voltage and frequency of the application (I
2
C bus specification Rev. 03, 19 June 2007).
Maxim Integrated
4
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Pin Configurations
TOP VIEW
SCL
SDA
SLPZ
N.C.
1
2
3
4
8
7
GND
IO
V
CC
N.C.
TOP MARK
+
+
1
SLPZ
2
SDA
3
SCL
“rr” = REVISION CODE
+
+
DS2483
EP
6
5
TDFN
(2mm
x
3mm)
2483
YMrr
TOP VIEW
V
CC
6
IO
5
GND
4
TOP MARK
DS2483
SOT23
3Grr
Pin Description
PIN
TDFN-EP
1
2
SOT23
3
2
NAME
SCL
SDA
FUNCTION
I
2
C Serial-Clock Input. Must be connected to the I
2
C bus supply voltage through a pullup
resistor.
I
2
C Serial-Data Input/Output. Must be connected to the I
2
C bus supply voltage through a pul-
lup resistor.
Power Supply for I
2
C Port and Active-Low Control Input to Activate the Low-Power Sleep
Mode. This pin can be driven directly by a push-pull port or by an open-drain port with a
2.2kI pullup resistor to the I
2
C voltage (V
CI2C
) over the entire operating voltage range.
No Connection. Not internally connected.
Power-Supply Input
Input/Output Driver for 1-Wire Line
Ground Reference
Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for proper operation.
Refer to
Application Note 3273: Exposed Pads: A Brief Introduction
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