ADVANCE
S25FL256L, S25FL128L
256 Mbit (32 Mbyte),128 Mbit (16 Mbyte)
3.0 V FL-L Flash Memory
Features
Serial Peripheral Interface (SPI) with Multi-I/O
Clock polarity and phase modes 0 and 3
Double Data Rate (DDR) option
Quad peripheral Interface (QPI) option
Extended Addressing: 24- or 32-bit address options
Serial Command subset and footprint compatible with S25FL-A,
S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI families
– Multi I/O Command subset and footprint compatible with S25FL-P,
S25FL-S and S25FS-S SPI families
–
–
–
–
–
Security features
–
–
–
–
Status and Configuration Register Protection
Four Security Regions of 256 bytes each outside the main Flash array
Legacy Block Protection: Block range
Individual and Region Protection
– Individual Block Lock: Volatile individual Sector/Block
– Pointer Region: Non-Volatile Sector/Block range
– Power Supply Lock-down, Password, or Permanent protection of
Security Regions 2 and 3 and Pointer Region
Read
– Commands: Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO, DDR
Quad I/O.
– Modes: Burst Wrap, Continuous (XIP), QPI
– Serial Flash Discoverable Parameters (SFDP) for configuration
information.
Technology
– 65nm Floating Gate Technology
Single Supply Voltage with CMOS I/O
– 2.7 V to 3.6 V
Temperature Range
– Industrial (
–
40
°
C to +85
°
C)
– Industrial Plus (
–
40
°
C to +105
°
C)
– Extended (
–
40°C to +125°C)
Program Architecture
– 256 Bytes Page Programming buffer
– Program suspend and resume
Erase Architecture
– Uniform 4KB Sector Erase
– Uniform 32KB Half Block Erase
– Uniform 64KB Block Erase
– Chip erase
– Erase suspend and resume
100,000 Program-Erase Cycles, min
20 Year Data Retention, typical
Packages (all Pb-free)
8-pin SOIC 208 mil (SOC008) - S25FL128L only
WSON 5
6 mm (WND008) - S25FL128L only
WSON 6
8 mm (WNH008) - S25FL256L
16-pin SOIC 300 mil (SO3016)
BGA-24 6
8 mm
– 5
5 ball (FAB024) footprint
– 4
6 ball (FAC024) footprint
– Known Good Die and Known Tested Die
–
–
–
–
–
Block Diagram
CS#
SCK
SI/IO0
SO/IO1
I/O
WP#/IO2
RESET#/IO3
RESET#
Data Path
Control
Logic
X Decoders
Memory Array
Y Decoders
Data Latch
Cypress Semiconductor Corporation
Document Number: 002-00124 Rev. **
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 07, 2015
S25FL256L, S25FL128L
Performance Summary
Maximum Read Rates SDR
Command
Read
Fast Read
Dual Read
Quad Read
Clock Rate (MHz)
50
133
133
133
MBps
6.25
16.5
33
66
Maximum Read Rates DDR
Command
DDR Quad Read
Clock Rate (MHz)
66
MBps
66
Typical Program and Erase Rates
Operation
Page Programming
4 KBytes Sector Erase
32 KBytes Half Block Erase
64 KBytes Block Erase
KBytes/s
854
80
168
237
Typical Current Consumption,
–
40°C to +85°C
Operation
Fast Read 5MHz
Fast Read 10 MHz
Fast Read 20 MHz
Fast Read 50 MHz
Fast Read 108 MHz
Fast Read 133 MHz
Quad I/O / QPI Read 108 MHz
Quad I/O / QPI Read 133 MHz
Quad I/O / QPI DDR Read 33MHz
Quad I/O / QPI DDR Read 66MHz
Program
Erase
Standby SPI
Standby QPI
Deep Power Down
Typical Current
10
10
10
15
25
30
25
30
15
30
40
40
20
60
2
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
Document Number: 002-00124 Rev. **
Page 2 of 153
ADVANCE
S25FL256L, S25FL128L
Contents
1.
1.1
1.2
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
3.
3.1
3.2
3.3
3.4
4.
4.1
4.2
4.3
4.4
4.5
5.
5.1
5.2
5.3
5.4
5.5
5.6
6.
6.1
6.2
7.
7.1
7.2
7.3
FL-L Family Overview..................................................
4
General Description ....................................................... 4
Migration Notes.............................................................. 5
Signal Descriptions
.....................................................
Input/Output Summary...................................................
Multiple Input / Output (MIO)..........................................
Serial Clock (SCK) .........................................................
Chip Select (CS#) ..........................................................
Serial Input (SI) / IO0 .....................................................
Serial Output (SO) / IO1.................................................
Write Protect (WP#) / IO2 ..............................................
IO3 / RESET# ................................................................
RESET# .........................................................................
Voltage Supply (V
DD
).....................................................
Supply and Signal Ground (V
SS
) ...................................
Not Connected (NC) ......................................................
Reserved for Future Use (RFU).....................................
Do Not Use (DNU) .........................................................
System Block Diagrams.................................................
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Data Protection ............................................................
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Latchup Characteristics ...............................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
Timing Specifications
................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics...............................................
DDR AC Characteristics ..............................................
Embedded Algorithm Performance Tables ..................
6
6
7
7
7
7
7
7
8
8
8
8
8
9
9
9
7.4
7.5
7.6
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
JEDEC JESD216 Serial Flash Discoverable
Parameters (SFDP) Space ........................................... 51
Security Regions Address Space ................................. 51
Registers....................................................................... 52
Data Protection
........................................................... 68
Security Regions........................................................... 68
Deep Power Down ........................................................ 69
Write Enable Commands .............................................. 69
Write Protect Signal ...................................................... 70
Status Register Protect (SRP1, SRP0)......................... 70
Array Protection ............................................................ 71
Individual and Region Protection .................................. 78
Commands
.................................................................. 83
Command Set Summary............................................... 83
Identification Commands .............................................. 89
Register Access Commands......................................... 92
Read Memory Array Commands ................................ 105
Program Flash Array Commands ............................... 114
Erase Flash Array Commands.................................... 116
Security Regions Array Commands............................ 123
Individual Block Lock Commands ............................... 125
Pointer Region Command........................................... 129
Individual and Region Protection (IRP) Commands ... 130
Reset Commands ....................................................... 135
Deep Power Down Commands................................... 136
Hardware Interface
11
11
12
17
21
22
22
22
23
24
26
29
29
29
30
33
38
40
10. Data Integrity
............................................................. 139
10.1 Endurance .................................................................. 139
10.2 Data Retention ............................................................ 139
11. Software Interface Reference
.................................. 140
11.1 JEDEC JESD216B Serial Flash Discoverable
Parameters ................................................................. 140
11.2 Device ID Address Map .............................................. 148
11.3 Initial Delivery State .................................................... 148
12. Ordering Information
................................................ 149
12.1 Ordering Part Number................................................. 149
Glossary
13.
Document History
..................................................... 152
Physical Interface
...................................................... 41
Connection Diagrams .................................................. 41
Physical Diagrams ....................................................... 44
Address Space Maps
.................................................
Overview ......................................................................
Flash Memory Array.....................................................
ID Address Space ........................................................
50
50
50
51
Software Interface
Document Number: 002-00124 Rev. **
Page 3 of 153
ADVANCE
S25FL256L, S25FL128L
1. FL-L Family Overview
1.1
General Description
Floating Gate technology
65 nm process lithography
The Cypress FL-L Family devices are Flash non-volatile memory products using:
The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output
(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral
Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address
and read data on both edges of the clock.
The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides
individual 4KB sector, 32KB half block, 64KB block, or entire chip erase.
By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match
or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.
The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These
memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM,
executing code directly (XIP), and storing re-programmable data.
Document Number: 002-00124 Rev. **
Page 4 of 153
ADVANCE
S25FL256L, S25FL128L
1.2
1.2.1
Migration Notes
Features Comparison
The FL-L family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P families.
Table 1.1
Cypress SPI Families Comparison
Parameter
Technology Node
Architecture
Release Date
Density
Bus Width
Supply Voltage
Normal Read Speed
Fast Read Speed
Dual Read Speed
Quad Read Speed
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector/Block Size
Parameter Sector Size
Sector / Block Erase Rate (typ.)
128Mb - 512Mb
x1, x2, x4
2.7 V - 3.6 V
6MB/s (50MHz)
16.5MB/s (133MHz)
33MB/s (133MHz)
66MB/s (133MHz)
66MB/s (66MHz)
256B
4KB / 32KB / 64KB
-
80 KB/s (4KB)
168 KB/s (32KB
237KB/s (64KB)
Page Programming Rate (typ.)
Security Region / OTP
Individual and Region Protection or
Advanced Sector Protection
Erase Suspend/Resume
Program Suspend/Resume
Operating Temperature
854KB/s (256B)
1024B
Yes
Yes
Yes
–40°C to +85°C
–40°C to +105°C
40°C to +125°C
Notes:
Refer to individual data sheets for further details
.
1.2 MB/s (256B)
1.5 MB/s (512B)
1024B
Yes
Yes
Yes
–40°C to +85°C
–40°C to +105°C
500 KB/s
FL-L
65nm
Floating Gate
FL-S
65nm
MirrorBit
®
Eclipse™
In Production
128Mb - 1Gb
x1, x2, x4
2.7 V - 3.6 V / 1.65 V - 3.6 V V
IO
6MB/s (50MHz)
17MB/s (133MHz)
26MB/s (104MHz)
52MB/s (104MHz)
80MB/s (80MHz)
256B / 512B
64KB / 256KB
4KB (option)
136 KB/s (4KB)
437 KB/s (64KB)
365 KB/s
768B (3
256B)
No
Yes
Yes
–40°C to +85°C
256B
4KB / 64KB
256B
64KB / 256KB
4KB
130 KB/s
FL1-K
90nm
Floating Gate
In Production
4Mb - 64Mb
x1, x2, x4
2.7 V - 3.6 V
6MB/s (50MHz)
13MB/s (108MHz)
26MB/s (108MHz)
52MB/s (108MHz)
FL-P
90nm
MirrorBit
®
In Production
32Mb - 256Mb
x1, x2, x4
2.7 V - 3.6 V
5MB/s (40MHz)
13MB/s (104MHz)
20MB/s (80MHz)
40MB/s (80MHz)
170 KB/s
506B
No
No
No
–40°C to +85°C
–40°C to +105°C
Document Number: 002-00124 Rev. **
Page 5 of 153
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