This device provides two factory-programmed default power-up
configurations burned into One-Time Programmable (OTP) memory.
The configuration to be used is selected by the CONFIG pin. The two
configurations are specified by the customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices. The two configurations may be completely independent of
one another.
One usage example might be to install the device on a line card with
two optional daughter cards: an OC-12 option requiring a 622.08MHz
LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet
option requiring a 125MHz LVPECL clock translated from the same
19.44MHz input reference.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured. However, these settings
would have to be re-written next time the device powers-up.
Q0
CLK_ACTIVE
nc
LF0
LF1
V
EE
V
CCA
HOLDOVER
CLK0BAD
CLK1BAD
XTALBAD
31
32
33
34
35
36
37
38
39
40
30 29 28 27 26 25 24 23 22 21
20
Q1
IDT8T49N203I
40 Lead VFQFN
6mm x 6mm x 0.925mm
K Package
Top View
19
18
17
16
15
14
13
12
11
1 2 3
V
CC
XTAL_IN
XTAL_OUT
4
CLK_SEL
5 6 7
V
CC
CLK0
nCLK0
8
V
EE
9 10
CLK1
nCLK1
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice
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FPGA/CPLD
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