MCP19110/11
Digitally-Enhanced Power Analog Controller
with Integrated Synchronous Driver
Synchronous Buck Features
• Input Voltage: 4.5V to 32V
• Output Voltage: 0.5V to 3.6V
- Greater than 3.6V requires external divider
• Switching Frequency: 100 kHz to 1.6 MHz
• Quiescent Current: 5 mA Typical
• High-Drive:
- +5V Gate Drive
- 1A/2A Source Current
- 1A/2A Sink Current
• Low-Drive:
- +5V Gate Drive
- 2A Source Current
- 4A Sink Current
• Peak Current Mode Control
• Differential Remote Output Sense
• Multi-Phase Systems:
- Master or Slave
- Frequency Synchronized
- Common Error Signal
• Multiple Output Systems:
- Master or Slave
- Frequency Synchronized
- AEC-Q100 Qualifie
d
• Configurable Parameters:
- Overcurrent Limit
- Input Undervoltage Lockout
- Output Overvoltage
- Output Undervoltage
- Internal Analog Compensation
- Soft Start Profile
- Synchronous Driver Dead Time
- Switching Frequency
• Thermal Shutdown
Microcontroller Features
• Precision 8 MHz Internal Oscillator Block:
- Factory Calibrated
• Interrupt Capable
- Firmware
- Interrupt-on-Change Pins
• Only 35 Instructions to Learn
• 4096 Words On-Chip Program Memory
• High Endurance Flash:
- 100,000 write Flash Endurance
- Flash Retention: >40 years
• Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation
• Programmable Code Protection
• In-Circuit Debug (ICD) via Two Pins (MCP19111)
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
• 11 I/O Pins and One Input-Only Pin (MCP19110)
- Three Open-Drain Pins
• 14 I/O Pins and One Input-Only Pin (MCP19111)
- Three Open-Drain Pins
• Analog-to-Digital Converter (ADC):
- 10-bit Resolution
- 12 Internal Channels
- Eight External Channels
• Timer0: 8-bit Timer/Counter with 8-Bit Prescaler
• Enhanced Timer1:
- 16-bit Timer/Counter with Prescaler
- Two Selectable Clock Sources
• Timer2: 8-Bit Timer/Counter with Prescaler
- 8-bit Period Register
• I
2
C Communication:
- 7-bit Address Masking
- Two Dedicated Address Registers
- SMBus/PMBus
TM
Compatibility
2013-2016 Microchip Technology Inc.
DS20002331D-page 1
MCP19110/11
TABLE 1:
24-Pin QFN
I/O
24-PIN SUMMARY
Interrupt
ANSEL
Pull-up
Timers
MSSP
A/D
Basic
Additional
Analog Debug Output
(1)
Sync. Signal In/Out
(2,
3)
—
—
—
—
—
—
—
Error Signal In/Out
(3)
—
Device Input Voltage
Gate Drive Supply Input
Voltage
Internal Regulator Output
Small Signal Ground
Large Signal Ground
Low-Side MOSFET
Connection
High-Side MOSFET
Connection
Switch Node
Floating Bootstrap Supply
Output Voltage
Differential Sense
Output Voltage
Differential Sense
Current Sense Input
Current Sense Input
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
GPB0
GPB1
GPB2
V
IN
V
DR
V
DD
GND
P
GND
LDRV
HDRV
PHASE
BOOT
+V
SEN
-V
SEN
+I
SEN
-I
SEN
Note 1:
2:
3:
4:
5:
1
2
3
5
8
7
6
5
9
23
24
11
14
18
10
12
13
16
15
17
21
22
20
19
Y
Y
Y
Y
N
N
N
N
N
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
AN0
AN1
AN2
AN3
—
—
—
—
—
AN4
AN5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T0CKI
—
—
—
—
IOC
IOC
IOC
INT
IOC
IOC
IOC
(4)
IOC
IOC
IOC
IOC
IOC
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
Y
Y
N
Y
(5)
N
N
N
Y
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MCLR
ICSPDAT
ICSPCLK
—
—
—
V
IN
V
DR
V
DD
GND
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCL
SDA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
The Analog Debug Output is selected when the ATSTCON<BNCHEN> bit is set.
Selected when device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0> bits
in the BUFFCON register.
Selected when device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits in
the BUFFCON register.
The IOC is disabled when MCLR is enabled.
Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
2013-2016 Microchip Technology Inc.
DS20002331D-page 3
MCP19110/11
TABLE 2:
28-Pin QFN
I/O
28-PIN SUMMARY
Interrupt
ANSEL
Pull-up
Timers
MSSP
A/D
Basic
Additional
Analog Debug Output
(1)
Sync. Signal In/Out
(2,
3)
—
—
—
—
—
—
—
Error Signal In/Out
(3)
—
—
Alternate Sync
Signal In/Out
(2,
3)
—
—
Device Input Voltage
Gate Drive Supply Input
Voltage
Internal Regulator Output
Small Signal Ground
Large Signal Ground
Low-Side MOSFET
Connection
High-Side MOSFET
Connection
Switch Node
Floating Bootstrap Supply
Output Voltage
Differential Sense
Output Voltage
Differential Sense
Current Sense Input
Current Sense Input
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
GPB0
GPB1
GPB2
GPB4
GPB5
GPB6
GPB7
V
IN
V
DR
V
DD
GND
P
GND
LDRV
HDRV
PHASE
BOOT
+V
SEN
-V
SEN
+I
SEN
-I
SEN
Note 1:
2:
3:
4:
5:
1
2
3
5
9
8
7
6
10
26
28
4
27
21
11
13
16
20
12
14
15
18
17
19
24
25
23
22
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
AN0
AN1
AN2
AN3
—
—
—
—
—
AN4
AN5
AN6
AN7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T0CKI
—
—
—
—
IOC
IOC
IOC
INT
IOC
IOC
IOC
(4)
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
Y
Y
N
Y
(5)
N
N
N
Y
Y
Y
Y
Y
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MCLR
—
—
—
—
—
ICSPDAT
ICDDAT
ICSPCLK
ICDCLK
—
—
V
IN
V
DR
V
DD
GND
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCL
SDA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
The Analog Debug Output is selected when the ATSTCON<BNCHEN> bit is set.
Selected when device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0> bits
in the BUFFCON register.
Selected when device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits in
the BUFFCON register.
The IOC is disabled when MCLR is enabled.
Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
2013-2016 Microchip Technology Inc.
DS20002331D-page 5