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854S204BGILF

Description
clock buffer 4 out lvpecl/lvds FANout buffer
Categorysemiconductor    Other integrated circuit (IC)   
File Size1MB,23 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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854S204BGILF Overview

clock buffer 4 out lvpecl/lvds FANout buffer

854S204BGILF Parametric

Parameter NameAttribute value
ManufactureIDT (Integrated Device Technology)
Product CategoryClock Buffe
RoHSYes
Number of Outputs2
Propagation Delay - Max0.5 ns
Supply Voltage - Max3.465 V
Supply Voltage - Mi3.135 V
Maximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 C
Package / CaseTSSOP-16
PackagingTube
Mounting StyleSMD/SMT
Factory Pack Quantity96
Supply Curre120 mA
Low Skew, Dual, Programmable 1-to-2
Differential-to-LVDS, LVPECL Fanout Buffer
ICS854S204I
DATA SHEET
General Description
The ICS854S204I is a low skew, high performance dual,
programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer.
The PCLKx, nPCLKx pairs can accept most standard differential
input levels. With the selection of SEL_OUT signal, outputs can be
selected be to either LVDS or LVPECL levels. The ICS854S204I is
characterized to operate from either a 2.5V or a 3.3V power supply.
Guaranteed output and bank skew characteristics make the
ICS854S204I ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
Two programmable differential LVDS or LVPECL output banks
Two differential clock input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, SSTL, CML
Maximum output frequency: 3GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx inputs
Output skew: 15ps (maximum)
Bank skew: 15ps (maximum)
Propagation delay: 500ps (maximum)
Additive phase jitter, RMS: 0.15ps (typical)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Power Supply Configuration Table
3.3V Operation
V
DD
= 3.3V
V
TAP
= nc
2.5V Operation
V
DD
= 2.5V
V
TAP
= 2.5V
SEL_OUT Function Table
SEL_OUT
0
1
Output Level
LVDS
LVPECL
Block Diagram
V
TAP
SEL_OUT
Pulldown
CLKA
Pulldown
nCLKA
Pullup
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
Pin Assignment
PCLKA
nPCLKA
QA0
nQA0
QA1
nQA1
V
TAP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nPCLKB
PCLKB
QB0
nQB0
QB1
nQB1
V
DD
SEL_OUT
CLKB
Pulldown
nCLKB
Pullup
ICS854S204I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS854S204BGI REVISION B NOVEMBER 18, 2011
1
©2011 Integrated Device Technology, Inc.

854S204BGILF Related Products

854S204BGILF
Description clock buffer 4 out lvpecl/lvds FANout buffer
Manufacture IDT (Integrated Device Technology)
Product Category Clock Buffe
RoHS Yes
Number of Outputs 2
Propagation Delay - Max 0.5 ns
Supply Voltage - Max 3.465 V
Supply Voltage - Mi 3.135 V
Maximum Operating Temperature + 85 C
Minimum Operating Temperature - 40 C
Package / Case TSSOP-16
Packaging Tube
Mounting Style SMD/SMT
Factory Pack Quantity 96
Supply Curre 120 mA
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