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874002AGLF

Description
clock synthesizer / jitter cleaner pci express jitter attenuator
Categorysemiconductor    Other integrated circuit (IC)   
File Size221KB,15 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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874002AGLF Overview

clock synthesizer / jitter cleaner pci express jitter attenuator

874002AGLF Parametric

Parameter NameAttribute value
ManufactureIDT (Integrated Device Technology)
Product CategoryClock Synthesizer / Jitter Cleane
RoHSYes
Number of Outputs3
Output LevelLVDS
Max Output Freq160 MHz
Input LevelHCSL, LVDS, LVHSTL, LVPACL, SSTL
Max Input Freq128 MHz
Supply Voltage - Max3.465 V
Supply Voltage - Mi3.135 V
Package / CaseTSSOP-20
PackagingTube
Maximum Operating Temperature+ 70 C
Maximum Power Dissipati699.93 mW
Minimum Operating Temperature0 C
Mounting StyleSMD/SMT
Factory Pack Quantity74
Supply Curre80 mA
PCI Express/Jitter Attenuator
874002
DATA SHEET
G
ENERAL
D
ESCRIPTION
The 874002 is a high performance Differential-to-LVDS Jitter
Attenuator designed for use in PCI Express systems. In
some PCI Express systems, such as those found in desktop
PCs, the PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a jitter attenuator may be required to attenuate
high frequency random and deterministic jitter components
from the PLL synthesizer and from the system board. The
874002 has 3 PLL bandwidth modes: 200kHz, 400kHz,
and 800kHz. The 200kHz mode will provide maximum jitter
attenuation, but with higher PLL tracking skew and spread
spectrum modulation from the motherboard synthesizer may
be attenuated. The 400kHz provides an intermediate band-
width that can easily track triangular spread profiles, while providing
good jitter attenuation. The 800kHz bandwidth provides the best
tracking skew and will pass most spread profiles, but the jitter
attenuation will not be as good as the lower bandwidth modes.
Because some 2.5Gb serdes have x20 multipliers while others
have than x25 multipliers, the 874002 can be set for 1:1 mode or
5/4 multiplication mode (i.e. 100MHz input/125MHz output) using
the F_SEL pin.
T h e 8 7 4 0 0 2 u s e s I D T ’s 3
r d
G e n e ra t i o n Fe m t o C l o ck
T M
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI Express
add-in cards.
F
EATURES
Two differential LVDS output pair
One differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 160MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum)
3.3V operating supply
Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
PLL B
ANDWIDTH
(T
YPICAL
)
BW_SEL
0 = PLL Bandwidth: 200kHz
Float = PLL Bandwidth: 400kHz (Default)
1 = PLL Bandwidth: 800kHz
B
LOCK
D
IAGRAM
OE
Pullup
F_SEL
Pulldown
BW_SEL
Float
0 = 200kHz
Float = 400kHz
1 = 800kHz
CLK
Pulldown
nCLK
Pullup
P
IN
A
SSIGNMENT
Output Divider
0 ÷5 (default)
1 ÷4
QA0
nQA0
Phase
Detector
VCO
490 - 640 MHz
QA1
nQA1
874002
20-Lead TSSOP
FB_IN
Pulldown
nFB_IN
Pullup
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
÷5 (fixed)
FB_OUT
nFB_OUT
MR
Pulldown
874002 REVISION A 7/16/15
1
©2015 Integrated Device Technology, Inc.
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