UG24Cxx Serial EEPROM
Description:
The UG24Cxx is a serial, read/write non-volatile memory device. The device uses the CMOS floating gate process,
and is organized in 128 ~ 2048 words and each word is 8 bits wide. The device includes hardware data protection to
protect entire memory cells. This is controlled by the state of Write Protect (WP) pin.
The UG24Cxx supports byte-wide data writes,partial page writes, and a maximum 8 bytes page write modes.
A maximum of 8 devices may be connected to and controlled by the I
2
C serial interface.
Features:
Operating voltage: 2.4V ~ 5.5V
Low power consumption
- Operation: 5mA max.
- Standby: 5µA max.
Memory organization
- 1Kb = 128x8
- 2Kb = 256x8
- 4Kb = 512x8
- 8Kb = 1024x8
- 16Kb = 2048x8
I
2
C Serial Interface
Write cycle time: 5ms max.
Write cycle time: 5ms max.
Automatic erase-before-write operation
Partial page write allowed
8-byte page write modes
Write operation with built-in timer
Hardware controlled write protection
40-year data retention
10
6
erase/write cycles per word
8-pin DIP/SOP/TSSOP package
Commercial temperature range
(0°C to + 70°C)
Industrial temperature range
(-40°C to +85°C)
Pin Configurations
Pin Name
A0 ~ A2
SDA
SCL
WP
NC
VSS
VCC
Pin Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
No Connection
Ground
Power
Part Identification & Ordering Information
Part Number
UG24C02NC-2.4
UG24C02NI-2.4
UG24C02TC-2.4
UG24C02TI-2.4
UG24C02DI-2.4
UG24C02DC-2.4
UG24C04NI-2.4
UG24C04NC-2.4
UG24C04TC-2.4
UG24C04TI-2.4
UG24C04DI-2.4
UG24C04DC-2.4
UG24C08NI-2.4
UG24C08NC-2.4
UG24C08TC-2.4
UG24C08TI-2.4
UG24C08DI-2.4
UG24C08DC-2.4
UG24C16NI-2.4
UG24C16NC-2.4
UG24C16TC-2.4
UG24C16TI-2.4
UG24C16DI-2.4
UG24C16DC-2.4
Memory
2Kb
2Kb
2Kb
2Kb
2Kb
2Kb
4Kb
4Kb
4Kb
4Kb
4Kb
4Kb
8Kb
8Kb
8Kb
8Kb
8Kb
8Kb
16Kb
16Kb
16Kb
16Kb
16Kb
16Kb
Package
SOIC/SOP
SOIC/SOP
TSSOP
TSSOP
DIP
DIP
SOIC/SOP
SOIC/SOP
TSSOP
TSSOP
DIP
DIP
SOIC/SOP
SOIC/SOP
TSSOP
TSSOP
DIP
DIP
SOIC/SOP
SOIC/SOP
TSSOP
TSSOP
DIP
DIP
Pin Assignment
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
UG24Cxx
Pin Layout
Revision History
Nov 21 , 2002
Rev - A Product brief released.
Temp.
Comm
Indust
Comm
Indust
Comm
Indust
Comm
Indust
Comm
Comm
Comm
Indust
Comm
Indust
Comm
Indust
Comm
Indust
Comm
Indust
Comm
Indust
Comm
Indust
Re-Tek- 1045
support@unigen.com
http://www.unigen.com,
1
45388 Warm Springs Blvd. Fremont, CA. 94539
TEL: (510) 668-2088
FAX: (510)661-2788
Customer Comment Line: 1-800-826-0808
UG24Cxx Serial EEPROM
Absolute Maximum Ratings
Item
Voltage on Any Pin Relative to Vss
Temperature Under Bias
Storage Temperature
Symbol
VIN
TBIAS
TSTG
Rating
-0.3 to +6.0
-40 to +85
-50 to +150
Unit
V
°C
°C
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extendeed periods may affect device reliability.
Dc Characteristics
Parameter
Operating Voltage
Operating Current
Operating Current
Input Low Voltage
Input High Voltage
Output Low Voltage Level
Input Leakage Current
Output Leakage Current
Standby Current
Standby Current
Test Conditions
Symbol
Vcc
ICC1
ICC2
VIL
VIH
VOL
ILI
ILO
ISB1
ISB2
2.4V
5V
5V
5V
2.4V
IOL=2.1mA
VOUT = 0 or Vcc
VIN = 0 or Vcc
VIN = 0 or Vcc
VIN = 0 or Vcc
5V
5V
Read at 100KHz
Write at 100KHz
Vcc
Conditions
Min
2.4
Type
Max.
5.5
2
5
Unit
V
mA
mA
V
V
V
µA
µA
µA
µA
-1
0.7 Vcc
0.3 Vcc
Vcc + 0.5
0.4
1
1
5
4
Capacitance
CIN
COUT
Input Capacitance (See Note)
Output Capacitance (See Note)
f = 1MHz 25°C
f = 1MHz 25°C
6
8
pF
pF
Note : Capacitance is periodically sample and not 100% tested.
Re-Tek- 1045
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45388 Warm Springs Blvd. Fremont, CA. 94539
TEL: (510) 668-2088
FAX: (510)661-2788
Customer Comment Line: 1-800-826-0808
UG24Cxx Serial EEPROM
A.C.Characteristics
Symbol
f
SK
t
HIGH
t
LOW
t
r
t
f
t
HD:STA
Parameter
Clock Frequency
Clock High Time
Clock Low Time
SDA and SCL Rise Time
SDA and SCL Fall Time
START Condition Hold Time
Note
Note
After this period the first
clock pulse is generated
4000
4000
4700
1000
300
600
StandardMode*
Remark
Min.
Max.
100
600
1200
300
300
Min.
Max.
400
kHz
ns
ns
ns
ns
ns
Ta = 0°C to + 70°C
VCC=5V±10%
Unit
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
AA
START Condition Setup Time
Data Input Hold Time
Data Input Setup Time
STOP Condition Setup Time
Output Valid from Clock
Only relevant for repeated
START condition
4000
0
200
4000
3500
600
0
100
600
900
ns
ns
ns
ns
ns
t
BUF
Bus Free Time
Time in which the bus
must be free before a
new transmission can
start
4700
1200
ns
t
SP
t
WR
Input Filter Time Constant
(SDA and SCL Pins)
Write Cycle Time
Noise suppression time
100
5
50
5
ns
ms
Note : These parameters are periodically sampled but not 100% tested
* The standard mode means V
CC
= 2.4V to 5.5V
For relative timing, refer to timing diagrams
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45388 Warm Springs Blvd. Fremont, CA. 94539
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FAX: (510)661-2788
Customer Comment Line: 1-800-826-0808
UG24Cxx Serial EEPROM
Functional Description
Serial clock (SCL)
The SCL input is used for positive edge clock data
into each EEPROM device and negative edge clock
data out of each device.
Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
A0, A1, A2
The A2, A1 and A0 pins are device address inputs
that are hard wired for the UG24C01/02/04/08/16
As many as eight 1K/2K/4K/8K/16K devices may
be addressed on a single bus system (the device
addressing is discussed in detail under the Device
Addressing section)
Write protect (WP)
The UG24C01/02/04/08/16 has a write protect pin
that provides hardware data protection. The write
protect pin allows normal read/write operations
when connected to the V
SS
. When the write protect
pin is connected to Vcc, the write protection feature
is enabled and operates as shown in the following
table.
WP Pin Status
At V
CC
At V
SS
Protect Array
Full Array (1K/2K/4K/8K/16K)
Normal Read/Write Operations
Device addressing
The 1K/2K/4K/8K/16K EEPROM devices all require
an 8-bit device address word following a start cond-
ition to enable the chip for a read or write operation.
The device address word consist of a mandatory one,
zero sequence for the first four most significant bits
(refer to the diagram showing the Device Address).
This is common to all the EEPROM device.
The next three bits are the A2 , A1 and A0 device
address bits for the 1K/2K/4K/8K/16K EEPROM.
These three bits must compare to their correspon-
ding hard-wired inputpins.
Changes in data line while the clock line is
high will be interpreted as a START or STOP
condition.
Start condition
A high-to- low transition of SDA with SCL
high is a start condition which must precede
any other command (refer to Start and Stop
Definition Timing diagram).
Stop condition
A low-to-high transition of SDA with SCL
high is a stop condition. After a read se-
quence, the stop command will place the
EEPROM in a standby power mode (refer
to Start and Stop Definition Timing Diagram).
Acknowledge
All addresses and data words are serially
transmitted to and from the EEPROM in
8-bit words. The EEPROM sends a zero to
acknowledge that it has received each word.
This happens during the ninth clock cycle.
Data allowed
to change
SDA
SCL
Start
condition
Address or
asknowledge
valid
Stop
condition
Memory organization
UG24C01/02/04/08/16 ,1K/2K/4K/8K/16K
Serial EEPROM
internally organized with
128 ~ 2048 8-bit words, the 1K/2K/4K/8K/16K
requires an 8-bit data word address for random
word addressing
Device operations
Clock and data transition
Data transfer may be initiated only when the bus
is not busy. During data transfer, the data line
must remain stable whenever the clock line is high.
Re-Tek- 1045
support@unigen.com
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5
45388 Warm Springs Blvd. Fremont, CA. 94539
TEL: (510) 668-2088
FAX: (510)661-2788
Customer Comment Line: 1-800-826-0808
Analog electronics
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