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879893AYILF

Description
clock generators & support products 12 lvcmos out clock generator
Categorysemiconductor    Other integrated circuit (IC)   
File Size188KB,16 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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879893AYILF Overview

clock generators & support products 12 lvcmos out clock generator

879893AYILF Parametric

Parameter NameAttribute value
ManufactureIDT (Integrated Device Technology)
Product CategoryClock Generators & Support Products
RoHSYes
Package / CaseTQFP-48
PackagingReel
Factory Pack Quantity250
Low Skew, 1-to-12 (IDCS)
LVCMOS/LVTTL Clock Generator
Datasheet
879893
General Description
The 879893 is a PLL clock driver designed specifically for redun-
dant clock tree designs. The device receives two LVCMOS/LVTTL
clock signals from which it generates 12 new LVCMOS/LVTTL
clock outputs. External PLL feedback is used to also provide zero
delay buffer performance.
The 879893 Intelligent Dynamic Clock Switch (IDCS) circuit
continuously monitors both input CLK signals. Upon detection of a
failure (CLK stuck HIGH or LOW for at least 1 period), the
nALARM for that CLK will be latched (LOW). If that CLK is the
primary clock, the IDCS will switch to the good secondary clock
and phase/frequency alignment will occur with minimal output
phase disturbance.
Features
Twelve LVCMOS/LVTTL outputs (two banks of six outputs);
One QFB feedback clock output
Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs
CLK0, CLK1 supports the following input types:
LVCMOS, LVTTL
Automatically detects clock failure
IDCS on-chip intelligent dynamic clock switch
Maximum output frequency: 200MHz
Output skew: 50ps (maximum), within bank
Cycle-to-cycle (FSEL3=0, V
DD
=3.3V±5%): 150ps (maximum)
Smooth output phase transition during clock fail-over switch
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For functional replacement part use 87973i
Simplified Block Diagram
nOE/MR
Pulldown
Pin Assignment
V
DD
nALARM_RST
REF_SEL
nPLL_EN
GND
FSEL0
FSEL1
GND
FSEL2
FSEL3
nOE/MR
6
D
Q
FSEL0 FSEL1 FSEL2 QA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷2
÷2
÷2
÷4
÷2
÷16
÷8
÷4
CLK0
CLK1
FB
REF_SEL
nMAN/A
nALARM_RST
nPLL_EN
Pulldown
Pulldown
0
REF
1
1
PLL
VCO R
ANGE
240MHz - 500MHz
FB
0
QA0:QA5
GND
QA0
QA1
V
DD
GND
QA2
QA3
V
DD
GND
QA4
QA5
V
DD
Pulldown
Pullup
Pullup
IDCS
÷2
0
D
1
Q
6
QB0:QB5
Pulldown
FSEL0 FSEL1 FSEL2 QB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷16
÷8
÷6
÷8
÷4
÷16
÷8
÷4
D
Q
QFB
FSEL[0:2]
Pulldown
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
20
41
42
19
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
GND
QFB
FB
nMAN/A
V
DD
CLK0
CLK1
V
DDA
nALARM0
nALARM1
CLK_IND
GND
V
DD
GND
QB0
QB1
V
DD
GND
QB2
QB3
V
DD
GND
QB4
QB5
V
DD
FSEL3
Pulldown
nALARM0
nALARM1
CLK_IND
879893
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2017 Integrated Device Technology, Inc.
1
Revision B, January 10, 2017

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