Low Skew, 1-to-6, Crystal-to-LVDS
Fanout Buffer
ICS8546-01
DATA SHEET
General Description
The ICS8546-01 is a low skew, high performance 1-to-6 Crystal
Oscillator-to-LVDS Fanout Buffer. The ICS8546-01 has selectable
crystal, single ended or differential clock inputs. The single-ended
clock input accepts LVCMOS or LVTTL input levels and translate
them to LVDS levels. The CLK1, nCLK1 pair can accept most
standard differential input levels. The output enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/ deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8546-01 ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
Six 3.3V or 2.5V LVDS outputs
Selectable crystal oscillator, differential CLK1, nCLK1 pair
or LVCMOS/LVTTL clock input
CLK1, nCLK1 pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL
Maximum output frequency: 266MHz
Crystal frequency range: 14MHz - 40MHz
Output skew: 55ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 2.45ns (maximum)
Full 3.3V or 2.5V supply modes
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN
Pullup
D
Q
CLK_SEL0
Pulldown
CLK_SEL1
Pulldown
LE
Pin Assignment
nQ2
Q2
V
DDO
nQ1
Q1
GND
nQ0
Q0
CLK_SEL0
XTAL_IN
XTAL_OUT
CLK_EN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q3
nQ3
V
DDO
Q4
nQ4
V
DD
Q5
nQ5
CLK_SEL1
nCLK1
CLK1
CLK0
XTAL_IN
Q0
OSC
XTAL_OUT
CLK0
Pulldown
CLK1
nCLK1
Pullup
Pulldown
00
nQ0
6 LVDS Outputs
01
ICS8546-01
Q5
nQ5
1X
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
ICS8546AG-01 REVISION A FEBRUARY 25, 2011
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©2011 Integrated Device Technology, Inc.
ICS8546-01 Data Sheet
LOW SKEW, 1-TO 6, CRYSTAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 22
4, 5
6
7, 8
9,
16
10,
11
12
13
14
15
17, 18
19
20, 21
23, 24
Name
nQ2, Q2
V
DDO
nQ1, Q1
GND
nQ0, Q0
CLK_SEL0,
CLK_SEL1
XTAL_IN,
XTAL_OUT
CLK_EN
CLK0
CLK1
nCLK1
nQ5, Q5
V
DD
nQ4, Q4
nQ3, Q3
Output
Power
Output
Power
Output
Input
Input
Input
Input
Input
Input
Output
Power
Output
Output
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Type
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Clock select pins. LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
Synchronizing clock enable. When HIGH, clock outputs follow clock input. When
LOW, the outputs are disabled. LVCMOS / LVTTL interface levels. See Table 3.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Differential output pair. LVDS interface levels.
Positive supply pin.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS8546AG-01 REVISION A FEBRUARY 25, 2011
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©2011 Integrated Device Technology, Inc.
ICS8546-01 Data Sheet
LOW SKEW, 1-TO 6, CRYSTAL-TO-LVDS FANOUT BUFFER
Function Tables
Table 3. Control Input Function Table
Inputs
CLK_EN
0
0
0
1
1
1
CLK_SEL1
0
0
1
0
0
1
CLK_SEL0
0
1
X
0
1
X
Selected Source
XTAL
CLK0
CLK1/nCLK1
XTAL
CLK0
CLK1/nCLK1
Q0:Q5
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Outputs
nQ0:nQ5
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in
Figure 1.
Disabled
nCLK1
CLK0, CLK1,
XTAL
Enabled
CLK_EN
nQ0:nQ5
Q0:Q5
Figure 1. CLK_EN Timing Diagram
ICS8546AG-01 REVISION A FEBRUARY 25, 2011
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©2011 Integrated Device Technology, Inc.
ICS8546-01 Data Sheet
LOW SKEW, 1-TO 6, CRYSTAL-TO-LVDS FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
10mA
15mA
87.8°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
70
90
Units
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
55
70
Units
V
V
mA
mA
ICS8546AG-01 REVISION A FEBRUARY 25, 2011
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©2011 Integrated Device Technology, Inc.
ICS8546-01 Data Sheet
LOW SKEW, 1-TO 6, CRYSTAL-TO-LVDS FANOUT BUFFER
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
Input Low Voltage
CLK0,
CLK_SEL[0:1]
CLK_EN
Input
Low Current
CLK0,
CLK_SEL[0:1]
CLK_EN
V
DD
= 3.465V
V
DD
= 2.625V
Input
High Current
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-5
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
IL
I
IH
I
IL
Table 4D. Differential DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
nCLK1
Input High Current
CLK1
nCLK1
I
IL
V
PP
V
CMR
Input Low Current
CLK1
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
-5
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4E. LVDS DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.15
1.35
Test Conditions
Minimum
300
Typical
400
Maximum
485
50
1.50
50
Units
mV
mV
V
mV
Table 4F. LVDS DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.15
1.35
Test Conditions
Minimum
250
Typical
350
Maximum
485
50
1.50
50
Units
mV
mV
V
mV
ICS8546AG-01 REVISION A FEBRUARY 25, 2011
5
©2011 Integrated Device Technology, Inc.
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