89H32NT8AG2ZCHLG datasheet, PDF

Datasheet> All Categories > semiconductor> Other integrated circuit (IC)> 89H32NT8AG2ZCHLG

89H32NT8AG2ZCHLG: Descriptionpci interface IC pciE switch; Categorysemiconductor Other integrated circuit (IC); File Size316KB，7 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/; Environmental Compliance

Download Datasheet Parametric Compare View All

89H32NT8AG2ZCHLG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	89H32NT8AG2ZCHLG	-	-	View	Buy Now

89H32NT8AG2ZCHLG Overview

pci interface IC pciE switch

89H32NT8AG2ZCHLG Parametric

Parameter Name	Attribute value
Manufacture	IDT (Integrated Device Technology)
Product Category	PCI Interface IC
RoHS	Yes
Type	Switch - PCIe
Maximum Clock Frequency	125 MHz
Number of Lanes	32 Lane
Number of Ports	8 P
Operating Supply Voltage	1 V, 2.5 V, 3.3 V
Maximum Operating Temperature	+ 70 C
Mounting Style	SMD/SMT
Package / Case	FCBGA-484
Data Bus Width	32/64 bi
Maximum Data Rate	256 Gbps
Minimum Operating Temperature	0 C
Packaging	Tray
Factory Pack Quantity	60
Versi	Gen2

Preview

Download Datasheet

View All

32-Lane 8-Port PCIe® Gen2

System Interconnect Switch with

Non-Transparent Bridging

89HPES32NT8AG2

Product Brief

The 89HPES32NT8AG2 is a member of the IDT family of PCI

Express® switching solutions. The PES32NT8AG2 is a 32-lane, 8-port

system interconnect switch optimized for PCI Express Gen2 packet

switching in high-performance applications, supporting multiple simulta-

neous peer-to-peer traffic flows. Target applications include multi-host or

intelligent I/O based systems where inter-domain communication is

required, such as servers, storage, communications, and embedded

systems. such as servers, storage, communications, and embedded

systems.

With Non-Transparent Bridging functionality and innovative Switch

Partitioning feature, the PES32NT8AG2 allows true multi-host or multi-

processor communications in a single device. Integrated DMA control-

lers enable high-performance system design by off-loading data transfer

operations across memories from the processors. Each lane is capable

of 5 GT/s link speed in both directions and is fully compliant with PCI

Express Base Specification 2.1.

Device Overview

Features

◆

High Performance Non-Blocking Switch Architecture

–

32-lane, 8-port PCIe switch with flexible port configuration

–

Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s

Gen1 operation

–

Delivers up to 32 GBps (256 Gbps) of switching capacity

–

Supports 128 Bytes to 2 KB maximum payload size

–

Low latency cut-through architecture

–

Supports one virtual channel and eight traffic classes

◆

Port Configurability

–

Eight x4 switch ports

•

Adjacent x4 ports can be merged to achieve x8 port widths

–

Automatic per port link width negotiation

(x8

→

x1)

–

Crosslink support

–

Automatic lane reversal

–

Per lane SerDes configuration

•

De-emphasis

•

Receive equalization

•

Drive strength

◆

Innovative Switch Partitioning Feature

–

Supports up to 8 fully independent switch partitions

–

Logically independent switches in the same device

–

Configurable downstream port device numbering

–

Supports dynamic reconfiguration of switch partitions

•

Dynamic port reconfiguration — downstream, upstream,

non-transparent bridge

•

Dynamic migration of ports between partitions

•

Movable upstream port within and between switch partitions

Non-Transparent Bridging (NTB) Support

–

Supports up to 8 NT endpoints per switch, each endpoint can

communicate with other switch partitions or external PCIe

domains or CPUs

–

6 BARs per NT Endpoint

•

Bar address translation

•

All BARs support 32/64-bit base and limit address translation

•

Two BARs (BAR2 and BAR4) support look-up table based

address translation

–

32 inbound and outbound doorbell registers

–

4 inbound and outbound message registers

–

Supports up to 64 masters

–

Unlimited number of outstanding transactions

◆

Multicast

–

Compliant with the PCI-SIG multicast

–

Supports 64 multicast groups

–

Supports multicast across non-transparent port

–

Multicast overlay mechanism support

–

ECRC regeneration support

◆

Integrated Direct Memory Access (DMA) Controllers

–

Supports up to 2 DMA upstream ports, each with 2 DMA chan-

nels

–

Supports 32-bit and 64-bit memory-to-memory transfers

•

Fly-by translation provides reduced latency and increased

performance over buffered approach

•

Supports arbitrary source and destination address alignment

•

Supports intra- as well as inter-partition data transfers using

the non-transparent endpoint

–

Supports DMA transfers to multicast groups

–

Linked list descriptor-based operation

–

Flexible addressing modes

•

Linear addressing

•

Constant addressing

◆

Quality of Service (QoS)

–

Port arbitration

•

Round robin

–

Request metering

•

IDT proprietary feature that balances bandwidth among

switch ports for maximum system throughput

–

High performance switch core architecture

•

Combined Input Output Queued (CIOQ) switch architecture

with large buffers

◆

Clocking

–

Supports 100 MHz and 125 MHz reference clock frequencies

◆

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 7

2009 Integrated Device Technology, Inc.

September 15, 2009

89H32NT8AG2ZCHLG Related Products

	89H32NT8AG2ZCHLG	89H32NT8AG2ZBHLI8	89H32NT8AG2ZCHL	89H32NT8AG2ZBHL	89H32NT8AG2ZCHLI	89H32NT8AG2ZBHLGI8
Description	pci interface IC pciE switch	pci interface IC pciE switch	pci interface IC pciE switch	pci interface IC pciE switch	pci interface IC pciE switch	pci interface IC pciE switch
Manufacture	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Product Category	PCI Interface IC	PCI Interface IC	PCI Interface IC	PCI Interface IC	PCI Interface IC	PCI Interface IC
RoHS	Yes	N	N	N	N	Yes
Type	Switch - PCIe	Switch - PCIe	Switch - PCIe	Switch - PCIe	Switch - PCIe	Switch - PCIe
Maximum Clock Frequency	125 MHz	125 MHz	125 MHz	125 MHz	125 MHz	125 MHz
Number of Lanes	32 Lane	32 Lane	32 Lane	32 Lane	32 Lane	32 Lane
Number of Ports	8 P	8 P	8 P	8 P	8 P	8 P
Operating Supply Voltage	1 V, 2.5 V, 3.3 V	1 V, 2.5 V, 3.3 V	1 V, 2.5 V, 3.3 V	1 V, 2.5 V, 3.3 V	1 V, 2.5 V, 3.3 V	1 V, 2.5 V, 3.3 V
Maximum Operating Temperature	+ 70 C	+ 85 C	+ 70 C	+ 70 C	+ 85 C	+ 85 C
Mounting Style	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
Package / Case	FCBGA-484	FCBGA-484	FCBGA-484	FCBGA-484	FCBGA-484	FCBGA-484
Data Bus Width	32/64 bi	32/64 bi	32/64 bi	32/64 bi	32/64 bi	32/64 bi
Maximum Data Rate	256 Gbps	256 Gbps	256 Gbps	256 Gbps	256 Gbps	256 Gbps
Minimum Operating Temperature	0 C	- 40 C	0 C	0 C	- 40 C	- 40 C
Packaging	Tray	Reel	Tray	Tray	Tray	Reel
Factory Pack Quantity	60	600	60	60	60	600
Versi	Gen2	Gen2	Gen2	Gen2	Gen2	Gen2

Recommended Resources

Analysis of the effect of short circuit protection circuit on inverter

5V/12V converter circuit

Soft start circuit diagram using capacitor

Boost circuit diagram with shutdown control

CMOS gate voltage controlled oscillator circuit

845ddr computer motherboard circuit diagram_26

A large reward is offered to the expert who can answer the question!: Hello everyone, I want to ask: I made a thin client system, and now there is a problem in the experiment on two PCs: after I transfer the nk.bin image from the host to the slave through the network, t...; blackholes522 Embedded System

How can young engineers become "experts"?: Have a strong curiosity. This is a necessary condition for becoming an expert. You like new things, like to get to the bottom of problems, and take research as fun. Those who muddle through, perfuncto...; wateras1 Talking

Altera SoC FPGA and Xilinx Zynq FPGA Performance Comparison: ...; chenzhufly FPGA/CPLD

About DM3730 EHCI driver Suspend and Resume issues in WCE system: WinCE6R3, BSP based on: BSP_WINCE_ARM_A8_01_02_00, CPU: DM3730, PHY: TUSB1210, connected to the CPU's USBHOST2 port, ULPI mode, USB port is not connected to any peripherals. EHCI driver is the standar...; KevinLi DSP and ARM Processors

Wake up after suspend and enter OEMPowerOff but cannot resume: In the environment of s3c2440+wince5.0, the suspend wake-up function was implemented. However, after waking up, the program ran into OEMPowerOff and restored the registers. After re-initializing the L...; tangcongfai Embedded System

CC1101 Carrier Monitoring Function: CC1101 has a carrier sense function. When the RSSI of the sync word exceeds a certain threshold or changes by more than a certain value, there will be a jump on GDOx. Has anyone used this function? Is...; woody_chen RF/Wirelessly

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components