19-4557; Rev 1; 3/11
76V, APD, Bias Output Stage with
Current Monitoring
General Description
The DS1842 integrates the discrete high-voltage com-
ponents necessary for avalanche photodiode (APD)
bias and monitor applications. A switch FET is used in
conjunction with an external DC-DC controller to create
a boost DC-DC converter. A current clamp limits cur-
rent through the APD and also features an external
shutdown. The device also includes a dual current mir-
ror to monitor the APD current.
♦
76V Maximum Boost Voltage
♦
Switch FET
♦
Current Monitor with a Wide 1µA to 2mA Range,
Fast 50ns Time Constant, and 10:1 and 5:1 Ratio
♦
2mA Current Clamp with External Shutdown
♦
Multiple External Filtering Options
♦
3mm x 3mm, 14-Pin TDFN Package with Exposed Pad
Features
DS1842
Applications
APD Biasing
GPON Optical Network Unit and Optical Line
Transmission
Ordering Information
PART
DS1842N+
DS1842N+T&R
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
14 TDFN-EP*
14 TDFN-EP*
Pin Configuration appears at end of data sheet.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP
= Exposed pad.
Typical Application Circuit
3.3V
LX
DS1842
SW
GATE
GND
FB
COMP
D2
CLAMP
CURRENT
LIMIT
MIROUT
ROSA
DS1875
APD
TIA
MIRIN
C
BULK
CURRENT MIRROR
MIR1
C
COMP
R
COMP
MIR2
EXTERNAL MONITOR
MON3
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
76V, APD, Bias Output Stage with
Current Monitoring
DS1842
ABSOLUTE MAXIMUM RATINGS
Voltage Range on GATE and CLAMP
Relative to GND...................................................-0.3V to +12V
Voltage Range on MIRIN, MIROUT,
MIR1, and MIR2 Relative to GND........................-0.3V to +80V
Voltage Range on LX Relative to GND...................-0.3V to +85V
Continuous Power Dissipation (T
A
= +70°C)
TDFN (derate 24.4mW/°C above +70°C).................1951.2mW
Operating Junction Temperature Range ...........-40°C to +150°C
Storage Temperature Range .............................-55°C to +135°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (θ
JA
) ............41°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ...................8°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(T
A
= -40°C to +85°C, unless otherwise noted.)
PARAMETER
Switching Frequency
FET Capacitance
FET Gate Resistance
FET On-Resistance
GATE Voltage
Switching Current
LX Voltage
LX Leakage
CLAMP Voltage
CLAMP Threshold
Maximum MIROUT Current
SYMBOL
f
SW
C
GATE
C
LX
R
G
R
DSON
V
GS
I
LX
V
LX
I
IL(LX)
V
CLAMP
V
CLT
I
MIROUT
CLAMP = low
CLAMP = high
I
MIROUT
= 1mA
MIR1 to MIROUT Ratio
K
MIR1
I
MIROUT
= 1μA
15V < V
MIRIN
< 76V
I
MIROUT
= 1mA
MIR2 to MIROUT Ratio
MIR1, MIR2 Rise Time (20%/80%)
Shutdown Temperature
Leakage on GATE and CLAMP
K
MIR2
t
RC
T
SHDN
I
IL
I
MIROUT
= 1μA
15V < V
MIRIN
< 76V
(Note 2)
(Note 3)
-1
30
+150
+1
ns
°C
μA
0.190
0.188
0.200
0.200
0.210
0.212
A/A
0.095
0.094
0.100
0.100
V
GATE
= 0V, V
LX
= 76V
-1
0
2
1.75
4
2.6
Duty cycle = 10%, f
SW
= 100kHz
V
GS
= 3V, I
D
= 170mA
V
GS
= 10V, I
D
= 170mA
0
V
GS
= 0V, V
DS
= 25V
f
SW
= 1MHz
CONDITIONS
MIN
0
40
90
22
4.6
3.7
10
8
11
680
80
+1
11
7
4
10
0.105
0.106
A/A
V
mA
V
μA
V
V
mA
μA
TYP
MAX
1.2
UNITS
MHz
pF
Note 2:
Rising MIROUT transition from 10µA to 1mA; V
MIRIN
= 40V, 2.5kΩ load.
Note 3:
Guaranteed by design; not production tested.
2
_______________________________________________________________________________________
76V, APD, Bias Output Stage with
Current Monitoring
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
DS1842
MIRIN vs. MIROUT CURRENT
(V
MIRIN
= 40V)
DS1842 toc01
MIRIN CURRENT vs. TEMPERATURE
(V
MIRIN
= 40V, I
MIROUT
= 250nA)
DS1842 toc02
MIRIN CURRENT vs. TEMPERATURE
(V
MIRIN
= 40V, I
MIROUT
= 2mA)
DS1842 toc03
10,000
100
90
80
MIRIN CURRENT (μA)
70
60
50
40
30
20
10
5
4
MIRIN CURRENT (mA)
MIRIN CURRENT (μA)
1000
3
2
100
1
10
1
10
100
1000
10,000
MIROUT CURRENT (μA)
0
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
0
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
MIR ERROR vs. TEMPERATURE
(I
MIROUT
= 1μA)
DS1842 toc04
MIR ERROR vs. TEMPERATURE
(I
MIROUT
= 1mA)
DS1842 toc05
MIR ERROR vs. MIROUT CURRENT
DS1842 toc06
2
2
2
1
ERROR (%)
ERROR (%)
1
1
MIR2
MIR2
0
0
ERROR (%)
MIR2
0
-1
MIR1
-2
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
-1
MIR1
-2
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
-1
MIR1
-2
1
10
100
1000
10,000
MIROUT CURRENT (μA)
MIR ERROR vs. MIRIN VOLTAGE
DS1842 toc07
MIROUT CLAMP CURRENT
vs. TEMPERATURE
DS1842 toc08
2
5
1
MIR2 1μA
ERROR (%)
MIR2 1mA
I
MIROUT
(mA)
MIR1 1μA
MIR1 1mA
4
3
0
2
-1
1
-2
10
20
30
40
50
60
70
80
MIRIN VOLTAGE (V)
0
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
_______________________________________________________________________________________
3
76V, APD, Bias Output Stage with
Current Monitoring
DS1842
Typical Operating Characteristics (continued)
(T
A
= +25°C, unless otherwise noted.)
FET ON-RESISTANCE vs. DRAIN CURRENT
DS1842 toc09
FET DRAIN CURRENT vs. DRAIN VOLTAGE
V
GS
= 10V
V
GS
= 5V
V
GS
= 3.6V
V
GS
= 3.0V
300
200
100
V
GS
= 2.5V
0
1
2
DRAIN VOLTAGE (V)
3
4
DS1842 toc10
7
V
GS
= 2.5V
6
V
GS
= 3.0V
R
DSON
(Ω)
700
600
500
I
DS
(mA)
400
5
V
GS
= 3.6V
4
V
GS
= 5V
3
1
10
I
DS
(mA)
100
1000
V
GS
= 10V
0
Pin Description
PIN
1
2
3
4,
9–12
5
6
7
8
13
14
—
NAME
MIR1
MIR2
N.C.
N.C.
CLAMP
GATE
GND
LX
MIRIN
MIROUT
EP
FUNCTION
Current Mirror Monitor Output, 10:1 Ratio
Current Mirror Monitor Output, 5:1 Ratio
No Connection. Can be connected to
GND for compatibility with the DS1842A.
No Connection. Not internally
connected.
Clamp Input. Disables the current mirror
output (MIROUT).
FET Gate Connection
Ground
FET Drain Connection. Connect to
switching inductor.
Current Mirror Input
Current Mirror Output. Connect to APD
bias pin.
Exposed Pad. Connect to ground.
MIROUT
LX
GATE
GND
CLAMP
CURRENT
LIMIT
DS1842
Block Diagram
MIRIN
CURRENT MIRROR
MIR1
MIR2
THERMAL
SHUTDOWN
4
_______________________________________________________________________________________
76V, APD, Bias Output Stage with
Current Monitoring
MIR1
CLAMP
REF
and the 10:1 mirror is used, then the correct resistor is
approximately 5kΩ. If both MIR1 and MIR2 are con-
nected together, the correct resistor is 1.6kΩ.
The mirror response time is dominated by the amount
of capacitance placed on the output. For burst-mode
Rx systems where the fastest response times are
required (approximately a 50ns time constant), a 3.3pF
capacitor and external op amp should be used to
buffer the signal sent to the ADC. For continuous mode
applications, a 10nF capacitor is all that is required on
the output.
DS1842
Current Clamp
Figure 1. Current Clamp from Current Feedback
Detailed Description
The DS1842 contains discrete high-voltage compo-
nents required to create an APD bias voltage and to
monitor the APD bias current. The device’s mirror out-
puts are a current that is a precise ratio of the output
current across a large dynamic range. The mirror
response time is fast enough to comply with GPON Rx
burst-mode monitoring requirements. The device has a
built-in current-limiting feature to protect APDs. The
APD current can also be shut down by CLAMP or ther-
mal shutdown. The internal FET is used in conjunction
with a DC-DC boost controller to precisely create the
APD bias voltage.
The DS1842 has a current clamping circuit to protect
the APD by limiting the amount of current from MIROUT.
There are three methods of current clamping available.
1) Internally Defined Current Limit
The device’s current clamp circuit automatically clamps
the current when it exceeds I
CLAMP
.
2) External Shutdown Signal
The CLAMP pin can completely shut down the current
from MIROUT. The CLAMP pin is active high.
3) Precise Level Set by External Feedback Circuit
A feedback circuit is used to control the level applied to
the CLAMP pin. Figure 1 shows an example feedback
circuit.
Thermal Shutdown
As a safety feature, the DS1842 has a thermal-shut-
down circuit that turns off the MIROUT and MIRIN cur-
rents when the internal die temperature exceeds
T
SHDN
. These currents resume after the device has
cooled.
Current Mirror
The DS1842 has two current mirror outputs. One is a
10:1 mirror connected at MIR1, and the other is a 5:1
mirror connected to MIR2.
The mirror output is typically connected to an ADC
using a resistor to convert the mirrored current into a
voltage. The resistor to ground should be selected such
that the maximum full-scale voltage of the ADC is
reached when the maximum mirrored current is
reached. For example, if the maximum monitored cur-
rent through the APD is 2mA with a 1V ADC full scale,
Switch FET and Diode
The DS1842 switching FET is designed to complement
the DS1875 controller’s built-in DC-DC boost controller.
Other DC-DC converters are also compatible, including
the MAX1932. APD biasing of 16V to 76V can be
achieved using the DS1842.
_______________________________________________________________________________________
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