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87946AYILFT

Description
clock generators & support products pll based clock generator
Categorysemiconductor    Other integrated circuit (IC)   
File Size132KB,11 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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87946AYILFT Overview

clock generators & support products pll based clock generator

87946AYILFT Parametric

Parameter NameAttribute value
ManufactureIDT (Integrated Device Technology)
Product CategoryClock Generators & Support Products
RoHSYes
Package / CaseTQFP-32
PackagingReel
Factory Pack Quantity1000
1-to-10 Low Skew,
1, 2
LVCMOS/LVTTL
3.3V Fanout Buffer
Datasheet
87946I
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
General Description
The 87946I is a low skew, ÷1, ÷2 LVCMOS Fanout Buffer. The
87946I has two selectable single ended clock inputs. The 87946I
has two selectable single ended clock inputs. The single ended clock
inputs accept LVCMOS or LVTTL input levels. The low impedance
LVCMOS outputs are designed to drive 50 series or parallel
terminated transmission lines. The effective fanout can be increased
from 10 to 20 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of
each bank. The outputs can be utilized in the ÷1, ÷2 or a combination
of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the
internal frequency dividers and also controls the active and high
impedance states of all outputs.
The 87946I is characterized at 3.3V core/3.3V output. Guaranteed
output and part-to-part skew characteristics make the 87946I ideal
for those clock distribution applications demanding well defined
performance and repeatability.
Features
Ten single-ended LVCMOS outputs, 7 typical output impedance
Selectable CLK0 and CLK1 LVCMOS clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
Maximum input/output frequency: 150MHz
Output skew: 350ps (maximum)
3.3V input, 3.3V outputs
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For drop-in replacement use 87946i-147
Block Diagram
CLK_SEL
Pulldown
CLK0
Pullup
CLK1
Pullup
DIV_SELA
Pulldown
0
1
DIV_SELB
Pulldown
0
1
DIV_SELC
Pulldown
MR/nOE
Pulldown
3
Pin Assignment
MR/nOE
GND
GND
V
DDA
V
DDA
QA0
QA1
QA2
0
1
÷1
÷2
0
1
3
QA[0:2]
CLK_SEL
V
DD
CLK0
CLK1
QB[0:2]
DIV_SELA
DIV_SELB
DIV_SELC
GND
4
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
9
V
DDC
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
QC2
GND
GND
QC0
QC1
V
DDC
QC3
GND
QB0
V
DDB
QB1
GND
QB2
V
DDB
V
DDC
QC[0:3]
87946I
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision C, September 20, 2016
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