256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)
Commercial
IDT72205LB10
IDT72215LB10
IDT72225LB10
IDT72235LB10
IDT72245LB10
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
HF
t
XO
t
XI
t
XIS
t
SKEW1
t
SKEW2(2)
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width
(2)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(3)
Output Enable to Output Valid
Output Enable to Output in High-Z
(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Asynchronous Programmable Almost-Full Flag
Clock to Programmable Almost-Empty Flag
Clock to Half-Full Flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Set-Up Time
Skew time between Read Clock & Write Clock forFull Flag
Skew time between Read Clock & Write Clock for
Empty Flag
Min.
—
2
10
4.5
4.5
3
0
3
0
10
8
8
—
0
3
3
—
—
—
—
—
—
3
3.5
5
5
Max.
100
6.5
—
—
—
—
—
—
—
—
—
—
15
—
6
6
6.5
6.5
17
17
17
6.5
—
—
—
—
Commercial & Industrial
(1)
IDT72205LB15
IDT72215LB15
IDT72225LB15
IDT72235LB15
IDT72245LB15
Min.
—
2
15
6
6
4
1
4
1
15
10
10
—
0
3
3
—
—
—
—
—
—
6.5
5
6
6
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
20
—
8
8
10
10
24
24
24
10
—
—
—
—
IDT72205LB25
IDT72215LB25
IDT72225LB25
IDT72235LB25
IDT72245LB25
Min.
—
2
25
10
10
6
1
6
1
25
15
15
—
0
3
3
—
—
—
—
—
—
10
10
10
10
Max.
40
15
—
—
—
—
—
—
—
—
—
—
25
—
12
12
15
15
26
26
26
15
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Industrial temperature range product for the 15ns and the 25ns speed grades are available as a standard device. All other speed grades are available by special order.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
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FPGA/CPLD
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