Data Sheet
26182.124D*
6810
DABiC-IV, 10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6810xA
The A6810– devices combine 10-bit CMOS shift registers, accom-
panying data latches and control circuitry with bipolar sourcing outputs
and pnp active pull downs. Designed primarily to drive vacuum-
fluorescent displays, the 60 V and -40 mA output ratings also allow
these devices to be used in many other peripheral power driver applica-
tions. The A6810– feature an increased data input rate (compared with
the older UCN/UCQ5810-F) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
serial-data input rates of at least 10 MHz .
A CMOS serial data output permits cascade connections in applica-
tions requiring additional drive lines. Similar devices are available as
the A6812– (20 bits) and A6818– (32 bits).
The A6810– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electro-
magnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANK-
ING input high. The pnp active pull-downs will sink at least
2.5 mA.
The A6810– are available in two temperature ranges for optimum
performance in commercial (suffix S-) or industrial (suffix E-) applica-
tions. They are provided in two package styles for through-hole DIP
(suffix -A) or minimum-area surface-mount SOIC (suffix -LW).
Copper lead frames, low logic-power dissipation, and low output-
saturation voltages allow all devices to source 25 mA from all outputs
continuously over the maximum operating temperature range.
OUT
8
OUT
7
OUT
6
CLOCK
GROUND
LOGIC
SUPPLY
STROBE
OUT
5
OUT
4
1
2
3
LATCHES
4
5
6
7
8
9
V
DD
ST
CLK
REGISTER
REGISTER
LATCHES
18
17
16
V
BB
15
14
BLNK
13
12
11
10
OUT
9
OUT
10
SERIAL
DATA OUT
LOAD
SUPPLY
SERIAL
DATA IN
BLANKING
OUT
1
OUT
2
OUT
3
Dwg. PP-029
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
°
C
Logic Supply Voltage, V
DD
...................
7.0 V
Driver Supply Voltage, V
BB
...................
60 V
Continuous Output Current Range,
I
OUT
.........................
-40 mA to +15 mA
Input Voltage Range,
V
IN
.......................
-0.3 V to V
DD
+ 0.3 V
Package Power Dissipation,
P
D
........................................
See Graph
Operating Temperature Range, T
A
(Suffix ‘E–’) ..................
-40
°
C to +85
°
C
(Suffix ‘S–’) ..................
-20
°
C to +85
°
C
Storage Temperature Range,
T
S
...............................
-55
°
C to +125
°
C
FEATURES
s
Controlled Output Slew Rate
s
High-Speed Data Storage
s
60 V Minimum
s
Improved Replacements
Output Breakdown
for TL4810–, UCN5810–,
s
High Data Input Rate
and UCQ5810–
s
PNP Active Pull-Downs
s
Low Output-Saturation Voltages
s
Low-Power CMOS Logic
and Latches
Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A or -LW). Always
order by complete part number, e.g.,
A6810SLW
.
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C (A6810S-) or over operating temperature
range (A6810E-), V
BB
= 60 V unless otherwise noted.
Limits @ V
DD
= 3.3 V
Characteristic
Output Leakage Current
Output Voltage
Symbol
I
CEX
V
OUT(1)
V
OUT(0)
Output Pull-Down Current
Input Voltage
I
OUT(0)
V
IN(1)
V
IN(0)
Input Current
I
IN(1)
I
IN(0)
Input Clamp Voltage
Serial Data Output Voltage
V
IK
V
OUT(1)
V
OUT(0)
Maximum Clock Frequency
Logic Supply Current
f
c
I
DD(1)
I
DD(0)
Load Supply Current
I
BB(1)
I
BB(0)
Blanking-to-Output Delay
t
dis(BQ)
t
en(BQ)
Strobe-to-Output Delay
t
p(STH-QL)
t
p(STH-QH)
Output Fall Time
Output Rise Time
Output Slew Rate
t
f
t
r
dV/dt
All Outputs High
All Outputs Low
All Outputs High, No Load
All Outputs Low
C
L
= 30 pF, 50% to 50%
C
L
= 30 pF, 50% to 50%
R
L
= 2.3 kΩ, C
L
≤
30 pF
R
L
= 2.3 kΩ, C
L
≤
30 pF
R
L
= 2.3 kΩ, C
L
≤
30 pF
R
L
= 2.3 kΩ, C
L
≤
30 pF
R
L
= 2.3 kΩ, C
L
≤
30 pF
I
OUT
=
±200 µA
V
IN
= V
DD
V
IN
= 0 V
I
IN
= -200
µA
I
OUT
= -200
µA
I
OUT
= 200
µA
Test Conditions
V
OUT
= 0 V
I
OUT
= -25 mA
I
OUT
= 1 mA
V
OUT
= 5 V to V
BB
Mln.
—
57.5
—
2.5
2.2
—
—
—
—
2.8
—
10*
—
—
—
—
—
—
—
—
2.4
2.4
4.0
—
Typ.
<-0.1
58.3
1.0
5.0
—
—
<0.01
<-0.01
-0.8
3.05
0.15
—
0.25
0.25
1.5
0.2
0.7
1.8
0.7
1.8
—
—
—
50
Max.
-15
—
1.5
—
—
1.1
1.0
-1.0
-1.5
—
0.3
—
0.75
0.75
3.0
20
2.0
3.0
2.0
3.0
12
12
20
—
Limits @ V
DD
= 5 V
Min.
—
57.5
—
2.5
3.3
—
—
—
—
4.5
—
10*
—
—
—
—
—
—
—
—
2.4
2.4
4.0
—
Typ.
<-0.1
58.3
1.0
5.0
—
—
<0.01
<-0.01
-0.8
4.75
0.15
—
0.3
0.3
1.5
0.2
0.7
1.8
0.7
1.8
—
—
—
50
Max.
-15
—
1.5
—
—
1.7
1.0
-1.0
-1.5
—
0.3
—
1.0
1.0
3.0
20
2.0
3.0
2.0
3.0
12
12
20
—
Units
µA
V
V
mA
V
V
µA
µA
V
V
V
MHz
mA
mA
mA
µA
µs
µs
µs
µs
µs
µs
V/µs
ns
Clock-to-Serial Data Out Delay t
p(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at T
A
= +25°C.
*Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V
DD
and Ground)
C
CLOCK
A
SERIAL
DATA IN
DATA
50%
B
50%
t
p(CH-SQX)
SERIAL
DATA OUT
D
STROBE
50%
50%
DATA
E
BLANKING
LOW = ALL OUTPUTS ENABLED
t
p(STH-QH)
t
p(STH-QL)
90%
OUT
N
DATA
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
BLANKING
50%
t
dis(BQ)
t
r
t
en(BQ)
OUT
N
10%
t
f
90%
50%
DATA
Dwg. WP-030A
A.
Data Active Time Before Clock Pulse
(Data Set-Up Time), t
su(D)
.........................................
25 ns
B.
Data Active Time After Clock Pulse
(Data Hold Time), t
h(D)
...............................................
25 ns
C.
Clock Pulse Width, t
w(CH)
...............................................
50 ns
D.
Time Between Clock Activation and Strobe, t
su(C)
.......
100 ns
E.
Strobe Pulse Width, t
w(STH)
.............................................
50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable; operation at high temperatures will
reduce the specified maximum clock frequency.
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
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