PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES ON OCTOBER 28, 2014
IDT5T929
FEATURES:
• Input frequency:
- For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, or 622.08MHz
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,
333.26MHz, or 666.52MHz
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,
312.5MHz, or 625MHz
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,
322.26MHz, or 644.53MHz
• Output frequency range selection
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on Q
OUT
• Regenerated input clock on Q
REG
• Lock indicator
• Power-down mode
• LVPECL or LVDS outputs
• Two modes of output frequency range
- Mode 0: Q
OUT
range 155.5 - 166.6MHz. Q
REG
is a regenerated version
of the input clock.
- Mode 1: Q
OUT
range 622 - 666.5MHz. Q
REG
is a regenerated version
of the input clock frequency.
• Hitless switchover
• Differential LVPECL, LVDS, or single-ended LVTTL input interface
• 2.375 - 3.465V core and I/O
• Available in VFQFPN package
• use Replacement part: 8T49N222B-dddNLGI
The IDT5T929 generates a high precision FEC (Forward Error Cor-
rection) or non-FEC source clock for SONET/SDH systems as well as a
source clock for Gigabit Ethernet systems. This device also has clock
regeneration capability: it creates a "clean" version of the clock input by
using the internal oscillator to square the input clock's rising and falling
edges and remove jitter. In the event that the main clock input fails, the
device automatically locks to a backup reference clock using a hitless
switchover mechanism.
This device detects loss of valid CLKIN and leaves the VCO of the PLL at
the last valid frequency while an alternate input REFIN is selected. If CLKIN
and REFIN are different frequencies, the multiplication factor will be adjusted to
retain the same output frequency.
The IDT5T929 can act as a translator from a differential LVPECL, LVDS, or
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T929-10
has LVDS outputs and the IDT5T929-30 has LVPECL outputs.
The two modes of output frequency range are controlled by the SELmode.
When SELmode is high or low, the Q
OUT
is a multiplied version of the input clock
while Q
REG
is a regenerated version of the input clock.
DESCRIPTION:
APPLICATIONS:
•
•
•
•
•
Terabit routers
Gigabit ethernet systems
SONET / SDH systems
Digital cross connects
Optical transceiver modules
FUNCTIONAL BLOCK DIAGRAM
CLKIN
CLKIN
INPUT
MUX
Q
REG
PLL
DIV
N
Q
REG
Q
OUT
DIV
M
Q
OUT
REFIN
REFIN
LOCK,
FREQ.
DETECTOR
CONTROL
LOGIC
PD
SEL
MODE
LOCK
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2013
Integrated Device Technology, Inc.
MAY 2013
DSC 6400/17
IDT5T929
PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
Q
OUT
Q
OUT
GND
GND
V
DD
V
DD
PD
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD
V
I
V
O
21
20
19
V
DD
GND
Q
REG
Q
REG
GND
V
DD
LOCK
Description
Power Supply Voltage
Input Voltage
Output Voltage
Junction Temperature
Storage Temperature
Max
–0.5 to +4.1
–0.5 to +4.1
–0.5 to V
DD
+0.5
150
–65 to +165
Unit
V
V
V
°C
°C
28
GND
CLKIN
CLKIN
GND
REFIN
REFIN
GND
1
2
3
4
5
6
7
8
27
26
25
24
23
22
T
J
T
STG
GND
18
17
16
15
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
9
10
11
12
13
14
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Typ.
2.5
—
Max.
3
—
Unit
pF
pF
TEST
TEST
V
DD
V
DD
SEL
MODE
V
DD
GND
VFQFPN
TOP VIEW
NOTE:
1. Capacitance applies to all inputs except SELmode.
RECOMMENDED OPERATING RANGE
Symbol
T
A
V
DD
V
T
Description
Ambient Operating Temperature
Power Supply Voltage
Termination Voltage (LVPECL)
Termination Voltage (LVDS)
Min.
–40
2.375
—
—
Typ.
+25
—
V
DD
– 2
1.2
Max.
+85
3.465
—
—
Unit
°C
V
V
2
IDT5T929
PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
INPUT FREQUENCY RANGE
(1)
19.4MHz - 20.9MHz
38.8MHz - 41.7MHz
77.7MHz - 83.4MHz
155.5MHz - 167MHz
311MHz - 334MHz
622MHz - 667MHz
NOTE:
1. The PLL will automatically detect the input frequency and adjust the multiply ratio to
generate the appropriate output frequency.
The
5T929
will lock to, and track, a valid CLKIN signal;
LOCK
will be low
when this has occurred. If CLKIN fails, the
5T929
PLL will smoothly switch
to lock to REFIN without generating any glitches on the output. The fact that
the PLL is locked to REFIN rather than CLKIN is indicated by a high state on
LOCK.
When a valid input is then applied to CLKIN, the
5T929
will smoothly
switch back to locking on CLKIN, and
LOCK
will go low.
LOCK
will also switch
to high should the frequency of CLKIN drift close to the limits of the VCO tuning
range.
LOCK
FREQUENCY DETECTOR
OUTPUT FREQUENCY RANGE
SELmode
L
H
Q
OUT
/Q
OUT
155.5 - 166.6
622 - 666.5
Q
REG
/Q
REG
regenerated CLKIN/CLKIN
regenerated CLKIN/CLKIN
Unit
MHz
MHz
PIN DESCRIPTION
Pin Name
CLKIN,
CLKIN
I/O
I
Type
Adjustable
(1)
Description
Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float
to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected
on the floating input.
Differential reference clock input. The reference clock input is used as an input to the PLL when CLKIN/CLKIN fails. Differential
or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL
threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the
floating input.
2 level input to select output frequency range for Q
OUT
/Q
OUT
and Q
REG
/Q
REG
(see Output Frequency Range table)
Power Down Control. Shuts off entire chip when LOW.
Differential clock output. LVPECL or LVDS outputs.
Regenerated clock output from CLKIN/CLKIN, LVPECL, or LVDS outputs.
LOW when PLL is locked to CLKIN, HIGH in all other conditions
Factory testing only. This pin should be left unconnected.
No connection
REFIN,
REFIN
I
Adjustable
(1)
SELmode
PD
Q
OUT
, Q
OUT
Q
REG
, Q
REG
LOCK
TEST
NC
V
DD
GND
I
I
0
0
0
2-level
(2)
LVTTL
Adjustable
(3)
Adjustable
(3)
LVTTL
PWR
PWR
Power Supply
Ground
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V LVTTL levels
Single-ended 2.5V LVTTL levels
Differential LVPECL levels
Differential LVDS levels
2. 2-level inputs are static inputs and must be tied to V
DD
or GND.
3. Outputs can be LVPECL or LVDS.
3
IDT5T929
PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
CLOCK INPUT/OUTPUT CONFIGURATION DESCRIPTION
Application
Non-FEC
REFIN (MHz)
19.44, 38.88, 77.76, 155.52, 311.04,
622.08
CKIN (MHz)
19.44
38.88
77.76
155.52
311.04
622.08
FEC
20.83, 41.66, 83.31, 166.63, 333.26,
666.52
20.83
41.66
83.31
166.63
333.26
666.52
10GE copper
19.53, 39.06, 78.12, 156.25, 312.5,
625
19.53
39.06
78.12
156.25
312.5
625
10GE optical
20.14, 40.28, 80.56, 161.13, 322.26,
644.53
20.14
40.28
80.56
161.13
322.26
644.53
SELmode
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
Q
REG
(MHz)
19.44
19.44
38.88
38.88
77.76
77.76
155.52
155.52
311.04
311.04
622.08
622.08
20.83
20.83
41.66
41.66
83.31
83.31
166.63
166.63
333.26
333.26
666.52
666.52
19.53
19.53
39.06
39.06
78.12
78.12
156.25
156.25
312.50
312.5
625
625
20.14
20.14
40.28
40.28
80.56
80.56
161.13
161.13
322.26
322.26
644.53
644.53
Q
OUT
(MHz)
155.52
622.08
155.52
622.08
155.52
622.08
155.52
622.08
155.52
622.08
155.52
622.08
166.63
666.52
166.63
666.52
166.63
666.52
166.63
666.52
166.63
666.52
166.63
666.52
156.25
625
156.25
625
156.25
625
156.25
625
156.25
625
156.25
625
161.13
644.53
161.13
644.53
161.13
644.53
161.13
644.53
161.13
644.53
161.13
644.53
4
IDT5T929
PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
(1,2)
Symbol
I
DD
_
PD
ΔI
DD
I
TOT
Parameter
Power Supply Current
Power Supply Current per Input HIGH
(LVTTL inputs only)
Total Power Supply Current
V
DD
= Max., Q
OUT
= 622MHz, All outputs unloaded
—
200
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. As a general requirement, these parts must be capable of operating at the maximum frequency under a nominal load at a reasonable operating temperature. That means that
these parts must not burn up under extended use in a typical application.
Test Conditions
V
DD
= Max.,
PD
= GND, All outputs unloaded
V
DD
= Max., V
IN
= 2.375V
Typ.
—
—
Max
50
100
Unit
μA
μA
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IHH
V
ILL
I
2
Parameter
Input HIGH Voltage Level
(1)
Input LOW Voltage Level
(1)
2-Level Input DC Current
Test Conditions
2-Level Inputs Only
2-Level Inputs Only
V
IN
= V
DD
V
IN
= GND
Min.
V
DD
– 0.4
—
—
–200
Max
—
0.4
200
—
Unit
V
V
μA
HIGH Level
LOW Level
NOTE:
1. These inputs are normally wired to V
DD
or GND. If these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and the PLL may
require additional t
AQ
time before all datasheet limits are achieved.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL
Symbol
I
IH
I
IL
V
IK
V
IN
V
IH
V
IL
Parameter
Input HIGH Current
Input LOW Current
Clamp Diode Voltage
DC Input Voltage
DC Input HIGH
DC Input LOW
Test Conditions
V
DD
= 3.465V
V
DD
= 3.465V
V
DD
= 2.375V, I
IN
= -18mA
Min.
—
—
—
- 0.3
1.7
—
Typ.
—
—
- 0.7
—
—
—
Max
±1
±1
- 1.2
+3.465
—
0.7
Unit
μA
V
V
V
V
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVPECL
(1)
Symbol
I
IN
V
CMR
V
DIF
V
OH
V
OL
V
SWING
Parameter
Input Current (CLKIN, REFIN)
Common Mode Input Voltage
Differential Voltage Required to Toggle Input
Output Voltage HIGH (terminated through 50Ω tied to V
DD
- 2V)
(2)
Output Voltage LOW (terminated through 50Ω tied to V
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