74LVT273
3.3 V octal D-type flip-flop
Rev. 03 — 10 September 2008
Product data sheet
1. General description
The 74LVT273 is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V.
This device has eight edge-triggered D-type flip-flops with individual D inputs and Q
outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independent of the clock or data inputs by a LOW voltage
level on the MR input. The device is useful for applications where only the true output is
required and the CP and MR are common elements.
2. Features
I
I
I
I
I
I
I
I
Eight edge-triggered D-type flip-flops
Buffered common clock and asynchronous master reset
Input and output interface capability to systems at 5 V supply
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Output capability: +64 mA/−32 mA
Latch-up protection
N
JESD78 Class II exceeds 500 mA
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
Live insertion/extraction permitted
Power-up reset
No bus current loading when output is tied to 5 V bus
I
I
I
I
NXP Semiconductors
74LVT273
3.3 V octal D-type flip-flop
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVT273D
74LVT273DB
74LVT273PW
74LVT273BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
Type number
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
4. Functional diagram
11
1
CP
MR
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
MR
1
mna763
C1
R
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
D0
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
1D
2
5
6
9
12
15
16
19
mna764
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
2 of 17
NXP Semiconductors
74LVT273
3.3 V octal D-type flip-flop
D0
D1
D2
D3
D
Q
D
Q
D
Q
D
Q
CP
FF1
R
D
CP
CP
FF2
R
D
CP
FF3
R
D
CP
FF4
R
D
MR
Q0
D4
D5
Q1
D6
Q2
D7
Q3
D
Q
D
Q
D
Q
D
Q
CP
FF5
R
D
CP
FF6
R
D
CP
FF7
R
D
CP
FF8
R
D
Q4
Q5
Q6
Q7
001aae056
Fig 3.
Logic diagram
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
3 of 17
NXP Semiconductors
74LVT273
3.3 V octal D-type flip-flop
5. Pinning information
5.1 Pinning
74LVT273
terminal 1
index area
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
GND
(1)
GND 10
CP 11
13 D4
12 Q4
MR
2
3
4
5
6
7
8
9
1
74LVT273
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
001aai737
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND 10
001aai738
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4.
Pin configuration for SO20 and (T)SSOP20
Fig 5.
Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
MR
Q0 to Q7
D0 to D7
GND
CP
V
CC
Pin description
Pin
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
Description
master reset input (active LOW)
data output
data input
ground (0 V)
clock pulse input (active on rising edge)
positive supply voltage
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
4 of 17
NXP Semiconductors
74LVT273
3.3 V octal D-type flip-flop
6. Functional description
Table 3.
Inputs
MR
L
H
H
H
[1]
Function selection
Outputs
CP
X
↑
↑
L
Dn
X
h
l
X
Qn
L
H
L
Q0
Reset (clear)
Load 1
Load 0
Retain state
Operating mode
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition;
X = Don’t care;
↑
= LOW-to-HIGH clock transition; Q0 = output as it was.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
total power dissipation
Conditions
[1]
Min
−0.5
−0.5
−0.5
−50
−50
-
−64
−65
[2]
Max
+4.6
+7.0
+7.0
-
-
128
-
+150
150
500
Unit
V
V
V
mA
mA
mA
mA
°C
°C
mW
Output in OFF or HIGH state
V
I
< 0 V
V
O
< 0 V
output in LOW state
output in HIGH state
[1]
-
T
amb
=
−40 °C
to +85
°C
[3]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
For SO20 packages: above 70
°C
derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
°C
derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
I
OH
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level output current
Conditions
Min
2.7
0
−32
Typ
-
-
-
Max
3.6
5.5
-
Unit
V
V
mA
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
5 of 17
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