ICS8633-01
1-
TO
-3 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES APRIL 25, 2015
G
ENERAL
D
ESCRIPTION
The ICS8633-01 is a high perfor mance 1-to-3
Differential-to-3.3V LVPECL Zero Delay Buffer. The ICS8633-
01 has two selectable clock inputs. The CLKx, nCLKx
pairs can accept most standard differential input levels.
Utilizing one of the outputs as feedback to the PLL, out-
put frequencies up to 700MHz can be regenerated with
zero delay with respect to the input. Dual reference clock
inputs suppor t redundant clock or multiple reference
applications.
F
EATURES
•
Three differential 3.3V LVPECL outputs
•
Selectable differential clock inputs
•
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Output frequency range: 31.25MHz to 700MHz
•
Input frequency range: 31.25MHz to 700MHz
•
VCO range: 250MHz to 700MHz
•
External feedback for “zero delay” clock regeneration
•
Cycle-to-cycle jitter: 25ps (maximum)
•
Output skew: 25ps (maximum)
•
PLL reference zero delay: 50ps ± 100ps
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in both standard and lead-free RoHs-compliant
packages
•
Functional replacement devices: 8735AY-31LF,
01LF and 8735BKI-01LF
8735BYI-
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
PLL_SEL
V
CC
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V
CC
nFB_IN
FB_IN
V
EE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CCA
V
EE
V
EE
V
CCO
V
CCO
Q2
nQ2
Q1
nQ1
Vcco
Vcco
Q0
nQ0
V
EE
ICS8633-01
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm body package
F Package
Top View
8633AF-01
www.idt.com
REV. B MAY 12, 2014
1
ICS8633-01
1-
TO
-3 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 11
3
4
5
6
7
8
9
Name
PLL_SEL
V
CC
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Input
Power
Input
Input
Input
Input
Input
Input
Input
Type
Pullup
Description
Selects between the PLL and the reference clock as the input to the dividers.
When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS / LVT-
TL interface levels.
Core supply pins.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Pulldown Non-inverting differential clock input.
Pullup
Pulldown
Inverting differential clock input.
Clock select input. When LOW, selects CLK0, nCLK0.
When HIGH, selects CLK1, nCLK1. LVCMOS / LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go
Pulldown
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Pullup
Feedback input to phase detector for regenerating clocks with “zero delay”.
10
MR
Input
12
nFB_IN
Input
Input
Power
Output
Power
Output
Output
Power
13
FB_IN
14, 15,
V
EE
26, 27
16, 17
nQ0, Q0
18, 19,
V
CCO
24, 25
20, 21
nQ1, Q1
22, 23
28
nQ2, Q2
V
CCA
Pulldown Feedback input to phase detector for regenerating clocks with “zero delay”.
Negative supply pins.
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pin.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL1
0
0
1
SEL0
0
1
0
Reference Frequency Range (MHz)*
250 - 700
125 - 350
62.5 - 175
Outputs
PLL_SEL = 1
PLL Enable Mode
Q0:Q2, nQ0:nQ2
÷1
÷1
÷1
÷1
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
Inputs
SEL1
0
0
1
1
SEL0
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q0:Q2, nQ0:nQ2
÷4
÷4
÷4
÷8
1
1
31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is
250MHz to 700MHz.
8633AF-01
www.idt.com
2
REV. B MAY 12, 2014
ICS8633-01
1-
TO
-3 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
49°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
150
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
SEL0, SEL1,
CLK_SEL, MR
PLL_SEL
I
IL
Input Low Current
SEL0, SEL1,
CLK_SEL, MR
PLL_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.15
1.3
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
V
EE
+ 0.5
V
CC
- 0.85
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
8633AF-01
www.idt.com
REV. B MAY 12, 2014
3
ICS8633-01
1-
TO
-3 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
- 2V.
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
IN
Parameter
Input Frequency
CLK0, nCLK0,
CLK1, nCLK1
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
700
700
Units
MHz
MHz
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
t
Parameter
Output Frequency
Propagation Delay; NOTE 1
PLL Reference Zero Delay; NOTE
2, 4
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
Output Rise/Fall Time
Test Conditions
PLL_SEL = 0V, ƒ
≤
700MHz
PLL_SEL = 3.3V
Minimum
2.8
-50
Typical
Maximum
700
4.9
Units
MHz
ns
ps
ps
ps
ps
ms
ps
%
(Ø)
sk(o)
jit(cc)
jit()
θ
50
150
25
25
±50
1
t
t
t
t
L
t
R
/ t
F
20% to 80% @ 50MHz
300
700
odc
Output Duty Cycle
47
53
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Phase jitter is dependent on the input source used.
NOTE 6: Characterized at VCO frequency of 622MHz.
8633AF-01
www.idt.com
4
REV. B MAY 12, 2014
ICS8633-01
1-
TO
-3 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
C
YCLE
-
TO
-C
YCLE
J
ITTER
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
P
ROPAGATION
D
ELAY
8633AF-01
P
HASE
J
ITTER
& S
TATIC
P
HASE
O
FFSET
www.idt.com
REV. B MAY 12, 2014
5
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