SY58603U
4.25Gbps Precision CML Buffer with Internal
Termination and Fail Safe Input
General Description
The SY58603U is a 2.5/3.3V, high-speed, fully
differential CML buffer optimized to provide less than
10ps
pp
total jitter. The SY58603U can process clock
signals as fast as 2.5GHz or data patterns up to
4.25Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC-coupled or DC-
coupled) as small as 100mV (200mV
pp
) without any
level-shifting or termination resistor networks in the
signal path. For AC-coupled input interface applications,
an integrated voltage reference (V
REF-AC
) is provided to
bias the V
T
pin. The output is 400mV CML, with
extremely fast rise/fall times guaranteed to be less than
85ps.
The SY58603U operates from a 2.5V ±5% supply or
3.3V ±10% supply and is guaranteed over the full
industrial temperature range (–40°C to +85°C). For
applications that require LVPECL or LVDS outputs,
consider the SY58604U and SY58605U, buffers with
800mV and 325mV output swings respectively. The
SY58603U is part of Micrel’s high-speed, Precision
®
Edge product line.
Data sheets and support documentation can be found
on Micrel’s web site at:
www.micrel.com.
Precision Edge
®
Features
•
Precision 400mV CML buffer
•
Guaranteed AC performance over temperature and
voltage:
– DC-to >4.25Gbps throughput
– <300ps propagation delay (IN-to-Q)
– <85ps rise/fall times
•
Fail Safe Input
– Prevents output from oscillating when input is
invalid
•
Ultra-low jitter design
– <1ps
RMS
cycle-to-cycle jitter
– <10ps
PP
total jitter
– <1ps
RMS
random jitter
– <10ps
PP
deterministic jitter
•
High-speed CML output
•
2.5V ±5% or 3.3V ±10% power supply operation
•
Industrial temperature range: –40°C to +85°C
•
Available in 8-pin (2mm x 2mm) DFN package
Applications
•
•
•
•
•
Data Distribution: OC-48, OC-48+FEC, XAUI
Backplane Buffering
SONET clock or data distribution
Fibre Channel clock or data distribution
Gigabit Ethernet clock or data distribution
Functional Block Diagram
Markets
•
•
•
•
•
•
•
Storage
ATE
Test and measurement
Enterprise networking equipment
High-end servers
Access
Metro area network equipment
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2007
M9999-082707-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58603U
Ordering Information
(1)
Part Number
SY58603UMG
SY58603UMGTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
(2)
Package
Type
DFN-8
DFN-8
Operating
Range
Industrial
Industrial
Package Marking
603 with Pb-Free
bar-line indicator
603 with Pb-Free
bar-line indicator
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
8-Pin DFN
Pin Description
Pin Number
1, 4
Pin Name
IN, /IN
Pin Function
Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of
this pair internally terminates with 50Ω
to the VT pin. If the input swing falls below a
certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a
stable output by latching the output to its last valid state. See “Input Interface
Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates to
VT pin. This pin provides a center-tap to a termination network for maximum
interface flexibility. See “Input Interface Applications” section.
Reference Voltage: This output biases to V
CC
–1.2V. It is used for AC-coupling input
IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with
0.01µF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Please
refer to the “Input Interface Applications” section for more details.
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
CML Differential Output Pair: Differential buffered output copy of the input signal.
The output swing is typically 400mV. See “CML Output Termination” section.
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to
the V
CC
pin as possible.
2
VT
3
VREF-AC
5
6, 7
8
GND
Exposed pad
/Q, Q
VCC
August 2007
2
M9999-082707-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58603U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ............................... –0.5V to +4.0V
Input Voltage (V
IN
) ....................................... –0.5V to V
CC
CML Output Voltage (V
OUT
) .......... V
CC
-1.0V to V
CC
+0.5V
Current (V
T
)
Source or sink on VT pin ............................. ±100mA
Input Current
Source or sink Current on (IN, /IN) ................ ±50mA
Current (V
REF
)
(4)
Source or sink current on V
REF-AC
.............. ±1.5mA
Maximum operating Junction Temperature .......... 125°C
Lead Temperature (soldering, 20sec.) .................. 260°C
Storage Temperature (T
s
) .................... –65°C to +150°C
Operating Ratings
(2)
Supply Voltage (V
IN
) ........................ +2.375V to +3.60V
Ambient Temperature (T
A
) ................... –40°C to +85°C
(3)
Package Thermal Resistance
DFN
Still-air (θ
JA
) ............................................ 93°C/W
Junction-to-board (ψ
JB
) .......................... 56°C/W
DC Electrical Characteristics
(5)
T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
CC
I
CC
R
DIFF_IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
IN_FSI
V
REF-AC
V
T_IN
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions
for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
ψ
JB
and
θ
JA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V
IN
(max) is specified when V
T
is floating.
7. V
IH
(min) not lower than 1.2V.
Parameter
Power Supply Voltage Range
Power Supply Current
Differential Input Resistance
(IN-to-/IN)
Input HIGH Voltage
(IN, /IN)
Input LOW Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
(|IN - /IN|)
Input Voltage Threshold that
Triggers FSI
Output Reference Voltage
Voltage from Input to V
T
Condition
Min
2.375
3.0
Typ
2.5
3.3
39
Max
2.625
3.6
50
110
V
CC
V
IH
–0.1
1.7
Units
V
mA
Ω
V
V
V
V
No load, max. V
CC
90
IN, /IN, Note 7
IN, /IN
see Figure 3a, Note 6
see Figure 3b
V
CC
–1.6
0
0.1
0.2
100
30
V
CC
–1.3
V
CC
–1.2
100
V
CC
–1.1
1.28
mV
V
V
August 2007
3
M9999-082707-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58603U
CML Output DC Electrical Characteristics
(7)
V
CC
= +2.5V ±5% or +3.3V ±10%, R
L
= 100Ω
across the outputs; T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
OH
V
OUT
V
DIFF_OUT
R
OUT
Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter
Output HIGH Voltage
Output Voltage Swing
Differential Output Voltage Swing
Output Source Impedance
Condition
R
L
= 50Ω
to V
CC
See Figure 3a
See Figure 3b
Min
V
CC
-0.020
325
650
45
Typ
V
CC
-0.010
400
800
50
Max
V
CC
Units
V
mV
mV
55
Ω
August 2007
4
M9999-082707-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY58603U
AC Electrical Characteristics
V
CC
= +2.5V ±5% or +3.3V ±10%, R
L
= 100Ω
across the outputs, Input t
r
/t
f
: <300ps; T
A
= –40°C to +85°C, unless
otherwise stated.
Symbol
f
MAX
t
PD
t
Skew
t
Jitter
Parameter
Maximum Frequency
Propagation Delay
Part-to-Part Skew
Data
Clock
t
r,
t
f
Random Jitter
Deterministic Jitter
Cycle-to-Cycle Jitter
Total Jitter
Output Rise/Fall Times
(20% to 80%)
Duty Cycle
Notes:
8.
9.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
Random jitter is measured with a K28.7 pattern, measured at
≤ f
MAX
.
Condition
NRZ Data
V
OUT
> 200mV
IN-to-Q
V
IN
: 100mV-200mV
V
IN
: 200mV-800mV
Note 8
Note 9
Note 10
Note 11
Note 12
At full output swing.
Differential I/O
Clock
Min
4.25
2.5
150
120
Typ
3
250
190
Max
Units
Gbps
GHz
350
300
100
1
10
1
10
ps
ps
ps
ps
RMS
ps
PP
ps
RMS
ps
PP
ps
%
30
47
50
85
53
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23
–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t
JITTER
_
CC
= T
n
–T
n+1
,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of
≤ f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
August 2007
5
M9999-082707-B
hbwhelp@micrel.com
or (408) 955-1690
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