74AUP1G80
Low-power D-type flip-flop; positive-edge trigger
Rev. 4 — 28 June 2012
Product data sheet
1. General description
The 74AUP1G80 provides the single positive-edge triggered D-type flip-flop. Information
on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock
transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74AUP1G80
Low-power D-type flip-flop; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP1G80GW
74AUP1G80GM
74AUP1G80GF
74AUP1G80GN
74AUP1G80GS
74AUP1G80GX
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
TSSOP5
XSON6
XSON6
XSON6
XSON6
X2SON5
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
Version
SOT353-1
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
1
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8
0.8
0.35 mm
SOT1115
SOT1202
SOT1226
4. Marking
Table 2.
Marking
Marking code
[1]
pT
pT
pT
pT
pT
pT
Type number
74AUP1G80GW
74AUP1G80GM
74AUP1G80GF
74AUP1G80GN
74AUP1G80GS
74AUP1G80GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
D
Q
4
1
2
CP
mna649
D
CP
001aac523
4
2
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74AUP1G80
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 28 June 2012
2 of 22
NXP Semiconductors
74AUP1G80
Low-power D-type flip-flop; positive-edge trigger
CP
C
C
C
C
D
TG
C
TG
C
Q
C
C
TG
TG
C
C
mna651
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
74AUP1G80
74AUP1G80
D
CP
1
2
5
V
CC
CP
2
5
n.c.
D
1
6
V
CC
80
GND
3
4
Q
4
001aac563
GND
3
Q
001aac522
Transparent top view
Fig 4.
Pin configuration SOT353-1
Fig 5.
Pin configuration SOT886
74AUP1G80
74AUP1G80
D
1
3
GND
CP
2
4
aaa-003008
5
V
CC
D
CP
GND
1
2
3
6
5
4
V
CC
n.c.
Q
Q
001aaf507
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT891, SOT1115 and
SOT1202
Fig 7.
Pin configuration SOT1226 (X2SON5)
74AUP1G80
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 28 June 2012
3 of 22
NXP Semiconductors
74AUP1G80
Low-power D-type flip-flop; positive-edge trigger
6.2 Pin description
Table 3.
Symbol
D
CP
GND
Q
n.c.
V
CC
Pin description
Pin
TSSOP5 and X2SON5 XSON6
1
2
3
4
-
5
1
2
3
4
5
6
data input
clock pulse input
ground (0 V)
data output
not connected
supply voltage
Description
7. Functional description
Table 4.
Input
CP
L
[1]
H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
Function table
[1]
Output
D
L
H
X
Q
H
L
q
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[1]
Max
+4.6
-
+4.6
-
+4.6
+20
50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
0.5
-
-
50
65
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP5 packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
74AUP1G80
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 28 June 2012
4 of 22
NXP Semiconductors
74AUP1G80
Low-power D-type flip-flop; positive-edge trigger
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode and Power-down mode
Conditions
Min
0.8
0
0
40
0
Max
3.6
3.6
3.6
+125
200
Unit
V
V
V
C
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 0.8 V to 3.6 V
I
O
=
1.1
mA; V
CC
= 1.1 V
I
O
=
1.7
mA; V
CC
= 1.4 V
I
O
=
1.9
mA; V
CC
= 1.65 V
I
O
=
2.3
mA; V
CC
= 2.3 V
I
O
=
3.1
mA; V
CC
= 2.3 V
I
O
=
2.7
mA; V
CC
= 3.0 V
I
O
=
4.0
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 0.8 V to 3.6 V
I
O
= 1.1 mA; V
CC
= 1.1 V
I
O
= 1.7 mA; V
CC
= 1.4 V
I
O
= 1.9 mA; V
CC
= 1.65 V
I
O
= 2.3 mA; V
CC
= 2.3 V
I
O
= 3.1 mA; V
CC
= 2.3 V
I
O
= 2.7 mA; V
CC
= 3.0 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
I
74AUP1G80
Conditions
Min
Typ
Max
-
-
-
-
Unit
V
V
V
V
0.70
V
CC
-
0.65
V
CC
-
1.6
2.0
-
-
-
-
V
CC
0.1
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.30
V
CC
V
0.35
V
CC
V
0.7
0.9
-
-
-
-
-
-
-
-
0.1
0.3
V
CC
0.31
0.31
0.31
0.44
0.31
0.44
0.1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
0.75
V
CC
-
input leakage current
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 28 June 2012
5 of 22
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