Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
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the references to Nexperia, as shown below.
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use
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Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
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- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
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Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
FEATURES
•
Wide supply voltage range of 1.2V to 3.6V
•
Complies with JEDEC standard no. 8-1A
•
Current drive
±
24 mA at 3.0 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
MULTIBYTE
TM
flow-through standard pin-out architecture
•
Low inductance multiple V
CC
and ground pins for minimum noise
and ground bounce
DESCRIPTION
The 74ALVCH16821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16821 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
•
All data inputs have bus hold
•
Output drive capability 50Ω transmission lines @ 85°C
QUICK REFERENCE DATA
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
F
max
GND = 0V; T
amb
= 25°C; t
r
= t
f
≤
2.5ns
PARAMETER
Propagation delay
nCP to nQ
n
Input capacitance
Power dissipation capacitance per buffer
Maximum clock frequency
CONDITIONS
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
Outputs enabled
Outputs disabled
TYPICAL
2.6
2.5
5.0
33
17
250
350
UNIT
ns
pF
pF
MHz
V
I
= GND to V
CC1
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
mW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVCH16821 DL
74ALVCH16821 DGG
NORTH AMERICA
ACH16821 DL
ACH16821 DGG
DWG NUMBER
SOT371-1
SOT364-1
1998 May 29
2
853-2066 19467
FPGA/CPLD
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