FM3808DK datasheet, PDF - EEWORLD Datasheet

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FM3808DK: Description256Kb Bytewide FRAM w/ Real-Time Clock; File Size189KB，28 Pages; ManufacturerETC

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FM3808DK Overview

256Kb Bytewide FRAM w/ Real-Time Clock

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Preliminary

FM3808

256Kb Bytewide FRAM w/ Real-Time Clock

Features

256K bit Ferroelectric Nonvolatile RAM

•

Organized as 32,752 x 8 bits

•

High Endurance 100 Billion (10

) Read/Writes

•

10 year Data Retention

•

NoDelay™ Writes

•

70 ns Access Time/ 130 ns Cycle Time

•

Built-in Low V

Protection

Real-Time Clock/Calendar Function

•

Clock Registers in Top 16 bytes of Address Space

•

Backup Power from External Capacitor or Battery

•

Tracks Seconds through Centuries in BCD Format

•

Tracks Leap Years through 2099

•

Runs from a 32.768 kHz Timekeeping Crystal

System Supervisor Function

•

Programmable Clock/Calendar Alarm

•

Programmable Watchdog Timer

•

Power Supply Monitor

•

Interrupt Output - Programmable active high/low

•

Control Settings Inherently Nonvolatile

•

Generates either Processor Reset or Interrupt

Low Power Operation

•

5V Operation for Memory and Clock Interface

•

Backup Voltage as low as 2.5V

•

25 mA I

Active Current

•

µA

BAK

Clock Backup Current

Description

The FM3808 combines a 256Kb FRAM array with a

real-time clock and a system supervisor function. An

external 32.768 kHz crystal drives the timekeeping

function. It maintains time and date settings in the

absence of system power through the user’s choice of

backup power source – either a capacitor or a battery.

In either case data in the memory array does not

depend on the backup source, it remains nonvolatile

in FRAM. In addition to timekeeping, the FM3808

includes a system supervisor to manage low V

power conditions and a watchdog timer function. A

programmable interrupt output pin allows the user to

select the supervisor functions and the polarity of the

signal.

Both the FRAM array and the timekeeping function

are accessed through the memory interface. The

upper 16-address locations of the memory space are

allocated to the timekeeping registers rather than to

memory. The FRAM array provides data retention

for 10 years in the absence of system power, and is

not dependent on the backup power source for the

clock. This eliminates system concerns over data loss

in a traditional battery-backed RAM solution. In

addition, clock and supervisor control settings are

implemented in FRAM rather than battery-backed

RAM, making them more dependable. The FM3808

offers guaranteed operation over an industrial

temperature range of -40°C to +85°C.

Pin Configuration

A11

A13

VBAK

INT

VDD

A14

A12

A10

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

Ordering Information

FM3808-70-T

70 ns access, 32-pin TSOP

FM3808DK

DIP module development kit

Documentation for the DIP module development kit is

available separately.

This is a product in sampling or pre-production phase of develop-

ment. Characteristic data and other specifications are subject to

change without notice.

Rev 1.1

May 2003

Ramtron International Corporation

1850 Ramtron Drive, Colorado Springs, CO 80921

(800) 545-FRAM, (719) 481-7000, FAX (719) 481-7058

www.ramtron.com

Page 1 of 28

FM3808

Address

7FF8h

Description

Control-Nonvolatile

OSCEN

Reserved

CALS

CAL.3

CAL.2

CAL.1

CAL.0

/OSCEN

Reserved

CALS

CAL.3-0

/Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling

the oscillator saves battery power during storage. On a no-battery power up, this bit is set to 1.

The

RTC will not run until the oscillator is enabled. Set this bit to 0 to activate the RTC.

Do not use. Should remain set to 0.

Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction

from the time-base. This bit is implemented in FRAM. Calibration is explained below

These four bits control the calibration of the clock. These bits are implemented in FRAM.

7FF7h

Watchdog Timer

WDS

WDW

WDT.5

WDT.4

WDT.3

WDT.2

WDT.1

WDT.0

WDS

/WDW

WDT.5-0

Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no

affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only.

Reading it always will return a 0.

Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT.5-0) so it cannot

be written. This allows the user to strobe the watchdog without disturbing the timeout value. Setting this

bit to 0 allows bits 5-0 to be written on the next write to the Watchdog register. The new value will be

loaded on the next internal watchdog clock after the write cycle is complete. This function is explained

in more detail in the watchdog Timer section below.

Watchdog Timeout selection. The watchdog timer interval is selected by the 6-bit value in this register.

It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or timeout value is 31.25

ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3Fh). Setting the watchdog timer

previous cycle.

7FF6h

Interrupts

WIE

AIE

PFE

ABE

H/L

P/L

Reserved

WIE

AIE

PFE

ABE

H/L

P/L

Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives

the INT pin as well as the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.

Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When

set to 0, the alarm match only affects the AF flag.

Power-Fail Enable. When set to 1, the power-fail monitor drives the pin as well as the PF flag. When set

to 0, the power-fail monitor affects only the PF flag.

Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function

even in battery backup mode. When set to 0, the alarm will occur only when VDD>VLO.

High/Low. When set to a 1, the INT pin is push/pull active high. When set to a 0, the INT pin is open

drain, active low.

Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source

for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until

the Flags/Control register is read.

7FF5h

Alarm – Date of the month

10 date.1

10 date.0

Date.3

Date.2

Date.1

Date.0

Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.

Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1

causes the match circuit to ignore the date value.

Rev 1.1

May 2003

Page 5 of 28

FM3808DK Related Products

	FM3808DK	FM3808	FM3808-70-T
Description	256Kb Bytewide FRAM w/ Real-Time Clock	256Kb Bytewide FRAM w/ Real-Time Clock	256Kb Bytewide FRAM w/ Real-Time Clock

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