FUJITSU SEMICONDUCTOR
DATA SHEET
DS705-00011-1v0-E
32-bit Microcontroller
FR Family FR81S
MB91520 Series
MB91F522B/D/F/J/K/L,MB91F523B/D/F/J/K/L,MB91F524B/D/F/J/K/L,
MB91F525B/D/F/J/K/L,MB91F526B/D/F/J/K/L
*
DESCRIPTION
The MB91520 series is a Fujitsu Semiconductor 32-bit microcontroller designed for automotive devices.
This series contains the FR81S CPU which is compatible with the FR family.
Note: FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Semiconductor
Limited.
*:This series is a composition of the kind that adds HB/JB/KB/LB/SB/UB/WB/YB to the end of the
above-mentioned each name of articles of presence, According to Presence of sub-clock, CSV initial value and
LVD initial value.
Please see "■ORDERING INFORMATION" for details.
FUJITSU SEMICONDUCTOR provides information facilitating product development via the following website.
The website contains information useful for customers.
http://edevice.fujitsu.com/micom/en-support/
Copyright
©
2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.4
MB91520 Series
FEATURES
FR81S CPU Core
· 32-bit RISC, load/store architecture, pipeline 5-stage structure
· Maximum operating frequency: 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied (PLL clock
multiplication system))
· General-purpose register : 32 bits × 16 sets
· 16-bit fixed length instructions (basic instruction), 1 instruction per cycle
· Instructions appropriate to embedded applications
· Memory-to-memory transfer instruction
· Bit processing instruction
· Barrel shift order etc.
· High-level language support instructions
· Function entry/exit instructions
· Register content multi-load and store instructions
· Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
· Branch instructions with delay slot
Overhead reduction during branch process
· Register interlock function
Easy assembler writing
· The support at the built-in / instruction level of the multiplier
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
· Interrupt (PC/PS saving)
6 cycles (16 priority levels)
· The Harvard architecture allows simultaneous execution of program and data access.
· Instruction compatibility with the FR Family
· Built-in memory protection function (MPU)
· Eight protection areas can be specified commonly for instructions and the data.
· Control access privilege in both privilege mode and user mode.
· Built-in FPU (floating point arithmetic)
· IEEE754 compliant
· Floating-point register 32-bit × 16 sets
Peripheral functions
· Clock generation (equipped with SSCG function)
· Main oscillation (4MHz to 16MHz)
· Sub oscillation (32kHz to 100kHz) or none sub oscillation
· PLL multiplication rate : 1 to 20 times
· Built-in program flash memory capacity
MB91F522:256+64KB
MB91F523:384+64KB
MB91F524:512+64KB
MB91F525:768+64KB
MB91F526:1024+64KB
· Flash memory for built-in data (WorkFlash) 64KB
· Built-in RAM capacity
· Main RAM
MB91F522:48KB
MB91F523:48KB
MB91F524:64KB
MB91F525:96KB
MB91F526:128KB
· Backup RAM 8KB
2
DS705-00011-1v0-E
MB91520 Series
· General-purpose ports:
MB91F52xB 44 sets (No sub oscillation), 42 sets (sub oscillation)
MB91F52xD 56 sets (No sub oscillation), 54 sets (sub oscillation)
MB91F52xF 76 sets (No sub oscillation), 74 sets (sub oscillation)
MB91F52xJ 96 sets (No sub oscillation), 94 sets (sub oscillation)
MB91F52xK 120 sets (No sub oscillation), 118 sets (sub oscillation)
MB91F52xL 152 sets (No sub oscillation), 150 sets (sub oscillation)
Included I
2
C open drain corresponding ports:16 sets
· External bus interface
· 22-bit address, 16-bit data
· DMA Controller
· Up to 16 channels can be started simultaneously.
· 2 transfer factors (Internal peripheral request and software)
· A/D converter (successive approximation type)
· 12-bit resolution : Max.48ch (32ch+16ch)
· Conversion time : 1μs
· D/A converter (R-2R type)
· 8-bit resolution : 2ch
· External interrupt input: 8 channels × 2 units total 16 channels
· Level ("H" / "L"), or edge detection (rising or falling) enabled
· Multi-function serial communication (built-in transmission/reception FIFO memory) : Max.12 channels
· 5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 Automotive input
< UART (Asynchronous serial interface) >
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· Parity or no parity is selectable.
· Built-in dedicated baud rate generator
· An external clock can be used as the transfer clock
· Parity, frame, and overrun error detection functions provided
· DMA transfer support
<CSIO (Synchronous serial interface) >
·
·
·
·
·
·
·
Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
SPI supported; master and slave systems supported; 5 to 16, 20, 24, 32-bit data length can be set.
Built-in dedicated baud rate generator (Master operation)
An external clock can be entered. (Slave operation)
Overrun error detection function is provided
DMA transfer support
Serial chip select SPI function
<LIN (Asynchronous Serial Interface for LIN) >
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· LIN protocol revision 2.1 supported
· Master and slave systems supported
· Framing error and overrun error detection
· LIN synch break generation and detection; LIN synch delimiter generation
· Built-in dedicated baud rate generator
· An external clock can be adjusted by the reload counter
· DMA transfer support
· Hard assist function
< I
2
C >
· 2 channels ch.3 , ch.4 Standard mode/high-speed mode supported.
· 6 channels ch.5 to ch.8, ch.10, ch.11 Standard mode supported.
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· Standard mode (Max. 100kbps) / high-speed mode (Max. 400kbps) supported
· DMA transfer supported (for transmission only)
DS705-00011-1v0-E
3
MB91520 Series
· CAN Controller (CAN) : 3 channels
· Transfer speed : Up to 1Mbps
· 128-transmission/reception message buffering : 1 channel (ch.0),
64-transmission/reception message buffering : 2 channels (ch.1 and ch.2)
· PPG: 16-bit × Max. 48 channels
· LED drive output 4 channels 11ch to 14ch
· Reload timer : 16-bit × Max.8 channels
· Free-run timer :
16-bit × 3 channels
32-bit × Max 3 channels
· Input capture :
16-bit × 4 channels (linked to the free-run timer)
32-bit × Max 6 channels (linked to the free-run timer)
· Output compare :
16-bit × 6 channels (linked to the free-run timer)
32-bit × Max 6 channels (linked to the free-run timer)
· Waveform generator : 6 channels
· Up/Down counter
· 8/16-bit Up/Down counter × 2 channels
· Real-time clock (RTC) (for day, hours, minutes, seconds)
· Main or sub oscillation frequency can be selected for the operation clock
· Calibration: Real-time clock (RTC) of the subclock drive
· The main clock to sub clock ratio can be corrected by setting the real-time clock prescaler
· Clock Supervisor
· Monitoring abnormality (by damaged quartz, etc.) of suboscillation (32kHz) (dual clock products)
of the outside and main oscillation (4 MHz)
· When abnormality is detected, it switches to the CR clock.
· Initial value ON/OFF can be selected by the part number.
· Base timer : Max.2 channels
· 16-bit timer
· Any of four PWM/PPG/PWC/reload timer functions can be selected and used
· A 32-bit timer can be used in 2 channels of cascade mode
· CRC generation
· Watchdog timer
· Hardware watchdog
· Software watchdog (possible to set the valid range for counter clearing)
· NMI (non-maskable interrupt)
· Interrupt controller
· Interrupt request batch read
· The interrupt existence from two or more peripherals can be read by a series of register.
· I/O relocation
· Peripheral function pins can be reassigned.
· Low-power consumption mode
· Sleep / Stop / Watch / Sub RUN mode
· Stop (power shutdown) / Watch (power shutdown) mode
· Power-on reset
· Low-voltage detection reset (independently monitor the external power supply and the internal power
supply)
· The external power supply can select initial value ON/OFF by the part number.
· Device Package : LQFP-176/144/120/100/80/64
· CMOS 90nm Technology
· Power supplies
· 5V Power supply
· The internal 1.2V is generated from 5V with the voltage step-down circuit.
4
DS705-00011-1v0-E
MB91520 Series
PRODUCT LINEUP
Product lineup comparison 64pins
MB91F522B
MB91F523B
MB91F524B
MB91F525B
MB91F526B
System Clock
Minimum instruction execution
time
Flash Capacity (Program)
Flash Capacity (Data)
RAM Capacity
External BUS I/F
(22address/16data/4cs)
DMA Transfer
16-bit Base Timer
Free-run Timer
Input capture
Output Compare
16-bit Reload Timer
PPG
Up/down Counter
Clock Supervisor
External Interrupt
A/D converter
D/A converter (8bit)
Multi-Function Serial Interface
CAN
Hardware Watchdog Timer
CRC Formation
Low-voltage detection reset
Flash Security
ECC Flash/WorkFlash
ECC RAM
Memory Protection Function
(MPU)
Floating point arithmetic (FPU)
Real Time Clock (RTC)
General-purpose port (#GPIOs)
SSCG
Sub clock
CR oscillator
OCD (On Chip Debug)
TPU (Timing Protection Unit)
Key code register
Waveform generator
NMI request function
Operation guaranteed temperature
(T
A
)
Power supply
Package
On chip PLL Clock multiple method
12.5ns (80MHz)
(256+64)KB
(384+64)KB
(512+64)KB
(768+64)KB
(1024+64)KB
(48+8)KB
64KB
(64+8)KB
None
(96+8)KB
(128+8)KB
16ch
None
16bit×3ch
32bit×1ch
16bit×4ch
32bit×5ch
16bit×6ch
32bit×4ch
7ch
16bit×21ch
2ch
Yes
8ch×2units
12bit×13ch (1unit)
12bit×13ch (1unit)
1ch
8ch
64msg×2ch/128msg×1ch
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
44 ports
Yes
Yes
Yes
Yes
Yes
Yes
6ch
Yes
-40°C to +125°C
2.7V to 5.5V
LQFP-64
DS705-00011-1v0-E
5
京公网安备 11010802033920号
EEWORLD
