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TJA1124AHG/0Z

Description
Interface Circuit
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size263KB,23 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

TJA1124AHG/0Z Overview

Interface Circuit

TJA1124AHG/0Z Parametric

Parameter NameAttribute value
package instruction,
Reach Compliance Codeunknown
Samacsys Confidence4
Samacsys StatusReleased
Samacsys PartID11412180
Samacsys Pin Count25
Samacsys Part CategoryIntegrated Circuit
Samacsys Package CategoryOther
Samacsys Footprint NameDHVQFN24 (SOT815-1)_2
Samacsys Released Date2020-02-14 22:45:55
Is SamacsysN
Interface integrated circuit typeINTERFACE CIRCUIT
Base Number Matches1
TJA1124
Quad LIN master transceiver
Rev. 1 — 8 May 2018
Product data sheet
1
General description
The TJA1124 is a quad Local Interconnect Network (LIN) master channel device.
It provides the interface between a LIN master protocol controller and the physical
bus in a LIN network. Each of the four channels contains a LIN transceiver and LIN
master termination. The TJA1124 is primarily intended for in-vehicle subnetworks using
baud rates up to 20 kBd and is compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A,
ISO 17987-4:2016 (12 V LIN) and SAE J2602-1.
The transmit data streams generated by the LIN master protocol controller are converted
by the TJA1124 into optimized bus signals shaped to minimize ElectroMagnetic Emission
(EME). The LIN bus output pins are pulled HIGH via internal LIN master termination
resistors. The receivers detect receive data streams on the LIN bus input pins and
transfer them to the microcontroller via pins RXD1 to RXD4.
Power consumption is very low in Low Power mode. However, the TJA1124 can still be
woken up via pins SLP and LIN1 to LIN4.
2
Features and benefits
2.1 General
Four LIN master channels in a single package:
LIN transceiver
LIN master termination consisting of a diode and a 1 kΩ ±10 % resistor
Compliant with:
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A
ISO 17987-4:2016 (12 V LIN)
SAE J2602-1
Very low current consumption in Low Power mode with wake-up via SLP or LIN pins
Option to control an external voltage regulator via the INHN output
Bus signal shaping optimized for baud rates up to 20 kBd
VIO input for direct interfacing with 3.3 V and 5 V microcontrollers
Passive behavior in unpowered state
Undervoltage detection
K-line compatible
Leadless DHVQFN24 package (3.5 mm × 5.5 mm) supporting improved Automated
Optical Inspection (AOI) capability
2.2 Protection
Excellent ElectroMagnetic Immunity (EMI)
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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