Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
FBL2031
FEATURES
•
Latched, registered or straight through in either A to B or B to A path
•
Drives heavily loaded backplanes with equivalent load
impedances down to 10Ω.
•
High drive 100mA BTL open collector drivers on B-port
•
Allows incident wave switching in heavily loaded backplane buses
•
Reduced BTL voltage swing produces less noise and reduces
power consumption
•
Glitch-free power up/power down operation
•
Low I
CC
current
•
Tight output skew
•
Supports live insertion
•
Pins for the optional JTAG boundary scan function are provided
•
High density packaging in plastic Quad Flatpack
•
5V compatible I/O on A-port
DESCRIPTION
The FBL2031 is a 9-bit latched/registered transceiver featuring a
latched, registered or pass-thru mode in either the A-to-B or B-to-A
direction.
The FBL2031 is intended to provide the electrical interface to a high
performance wired-OR bus.
•
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
•
Compatible with IEEE Futurebus+ or proprietary BTL backplanes
•
Each BTL driver has a dedicated Bus GND for a signal return
•
Controlled output ramp and multiple GND pins minimize ground
bounce
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
t
PLH
t
PHL
C
O
I
OL
I
CC
Propagation delay
An to Bn
Propagation delay
Bn to An
Output capacitance (B0 – Bn only)
Output current (B0 – Bn only)
AIn to Bn (outputs Low or High)
Supply current
Bn to AOn (outputs Low)
Bn to AOn (outputs High)
PARAMETER
TYPICAL
2.7
4.4
4.2
6
100
11
22
18
mA
UNIT
ns
ns
pF
mA
ORDERING INFORMATION
PACKAGE
52-pin Plastic Quad Flat Pack (PQFP)
V
CC
= 3.3V±10%; T
amb
= –40°C to +85°C
FBL2031BB
DWG No.
SOT379-1
2000 Apr 18
2
853-2118 23499
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
FBL2031
PIN CONFIGURATION
TMS (option)
TCK (option)
LOGIC GND
BUS GND
BIAS V
OEB0
OEB1
VCC
OEA
VCC
A1
A0
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND
A2
LOGIC GND
A3
LOGIC GND
A4
LOGIC GND
A5
LOGIC GND
A6
LOGIC GND
A7
LOGIC GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
A8
SEL1
16 17 18 19 20 21 22 23 24 25 26
TDI (option)
TDO (option)
BUS GND
BG GND
BG VCC
SEL0
LCBA
LCAB
VCC
B8
B7
39
38
37
36
BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND
B5
BUS GND
B6
BUS GND
9-Bit latched/registered transceiver
FBL2031
B0
35
34
33
32
31
30
29
28
27
52-lead PQFP
SG00087
PIN DESCRIPTION
SYMBOL
A0 – A8
B0 – B8
OEB0
OEB1
OEA
BUS GND
LOGIC GND
V
CC
BIAS V
BG V
CC
BG GND
SEL0
SEL1
LCAB
LCBA
TMS
TCK
TDI
TDO
PIN NUMBER
50, 52, 2, 4, 6, 8, 10, 12, 14
40, 38, 36, 34, 32,
30, 28, 26, 24
46
45
47
25, 27, 29, 31, 33,
35, 37, 39, 41
51, 1, 3, 5, 7, 9, 11, 13
23, 43, 49
48
17
19
20
15
18
16
42
44
22
21
TYPE
I/O
I/O
Input
Input
Input
GND
GND
Power
Power
Power
GND
Input
Input
Input
Input
Input
Input
Input
Output
NAME AND FUNCTION
BiCMOS data inputs/3-State outputs (TTL)
Data inputs/Open Collector outputs, High current drive (BTL)
Enables the B outputs when High
Enables the B outputs when Low
Enables the A outputs when High
Bus ground (0V)
Logic ground (0V)
Positive supply voltage
Live insertion pre-bias pin
Band Gap threshold voltage reference
Band Gap threshold voltage reference ground
Mode select
Mode select
A to B clock/latch enable (transparent latch when Low)
B to A clock/latch enable (transparent latch when Low)
Test Mode Select (optional, if not implemented then no connect)
Test Clock (optional, if not implemented then no connect)
Test Data In (optional, if not implemented then no connect)
Test Data Out (optional, if not implemented then shorted to TDI)
2000 Apr 18
3
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
FBL2031
DESCRIPTION
The TTL-level side (A port) has a common I/O. The common I/O,
open collector B port operates at BTL signal levels. The logic
element for data flow in each direction is controlled by two mode
select inputs (SEL0 and SEL1). A “00” configures latches in both
directions. A “10” configures thru mode in both directions. A “01”
configures register mode in both directions. A “11” configures
register mode in the A-to-B direction and latch mode in the B-to-A
direction.
When configured in the buffer mode, the inverse of the input data
appears at the output port. In the register mode, data is stored on
the rising edge of the appropriate clock input (LCAB or LCBA). In the
latch mode, clock pins serve as transparent-Low latch enables.
Regardless of the mode, data is inverted from input to output.
The 3-State A port is enabled by asserting a High level on OEA. The
B port has two output enables, OEB0 and OEB1. Only when OEB0
is High and OEB1 is Low is the output enabled.
When either OEB0 is Low or OEB1 is High, the B port is inactive
and is pulled to the level of the pull-up voltage. New data can be
entered in the register and latched modes or can be retained while
the associated outputs are in 3-State (A port) or inactive (B port).
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
The B-port interfaces to “Backplane Transceiver Logic” (see the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading by placing an internal series diode on the
drivers. BTL also provides incident wave switching, a necessity for
high performance backplanes.
Output clamps are provided on the BTL outputs to further reduce
switching noise. The “V
OH
” clamp reduces inductive ringing effects
during a Low-to-High transition. The “V
OH
” clamp is always active.
The other clamp, the “trapped reflection” clamp, clamps out ringing
below the BTL 0.5V V
OL
level. This clamp remains active for
approximately 100ns after a High-to-Low transition.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch- free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while V
CC
is Low. The BIAS V pin is a low current input
which will reverse-bias the BTL driver series Schottky diode, and
also bias the B port output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with IEEE BTL Standard
1194.1. If live insertion is not a requirement, the BIAS V pin should
be tied to a V
CC
pin.
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be
infrequent and impossible to troubleshoot.
As with any high power device, thermal considerations are critical. It
is recommended that airflow (300Ifpm) and/or thermal mounting be
used to ensure proper junction temperature.
PACKAGE THERMAL CHARACTERISTICS
PARAMETER
θja
θja
θjc
Still air
300 Linear feet per minute air flow
Thermally mounted on one side to heat sink
CONDITION
52-PIN PLASTIC QFP
80°C/W
58°C/W
20°C/W
2000 Apr 18
4
Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
FBL2031
FUNCTION TABLE
MODE
An to Bn thru mode
An to Bn transparent latch
An to Bn latch and read
Bn outputs latched and read
(preconditioned latch)
An to Bn register
Bn to An thru mode
INPUTS
An
L
H
L
H
l
h
X
l
h
—
—
—
Bn to An transparent latch
—
—
—
—
Bn to An latch and read
—
—
—
An outputs latched and read
(preconditioned latch)
—
—
—
—
X
X
X
Bn*
—
—
—
—
—
—
—
—
—
L
H
L
H
L
H
l
h
l
h
X
X
l
h
X
X
X
OEB0
H
H
H
H
H
H
H
H
H
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
X
X
X
X
OEB1
L
L
L
L
L
L
L
L
L
OEA
L
L
L
L
L
L
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
LCAB
X
X
L
L
↑
↑
H
↑
↑
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LCBA
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
↑
↑
↑
↑
H
H
↑
↑
X
X
X
SEL0
H
H
L
L
L
L
L
X
X
H
H
L
L
H
H
L
L
H
H
L
H
L
L
X
X
X
SEL1
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
H
H
L
H
H
H
X
X
X
OUTPUTS
An
input
input
input
input
input
input
X
input
input
H
L
H
L
H
L
H
L
H
L
latched
data
latched
data
H
L
X
X
Z
Bn
H**
L
H**
L
H**
L
latched
data
H**
L
input
input
input
input
input
input
input
input
input
input
X
X
input
input
H**
H**
X
Bn to An register
Disable Bn outputs
Disable An outputs
Disable
Disable
L
X
X
X
H
X
FUNCTION SELECT TABLE
MODE SELECTED
Thru mode
Register mode (An to Bn)
Latch mode (An to Bn)
Register mode (Bn to An)
Latch mode (Bn to An)
NOTES:
H = High voltage level
L
= Low voltage level
l
= Low voltage level one set-up time prior to the Low-to-High
LCXX transition
h
= High voltage level one set-up time prior to the Low-to-High
LCXX transition
X = Don’t care
SEL0
H
X
L
L
L
H
Z
—
↑
H**
Bn*
=
=
=
=
=
SEL1
L
H
L
H
L
H
High-impedance (OFF) state
Input not externally driven
Low-to-High transition
Goes to level of pull-up voltage
Precaution should be taken to ensure B inputs do not float.
If they do, they are equal to Low state.
Disable = OEB0 is Low or OEB1 is High.
2000 Apr 18
5
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