FQV01 · FQV02 · FQV03 · FQV04 · FQV05
3.3 Volt Asynchronous x9 First-In/First-Out Queue
Document Title
3.3 Volt Asynchronous x9 First-In/First-Out Queue
Revision History
Rev. No.
C
D
FlexQ
TM
Async
History
Page 1, 2, 5, 6, 7, 8, 13, 14
Add Pb-free package type on page 14
Issue Date
August 1, 2003
May 8, 2006
Remark
(May, 2006, Version D)
AMIC Technology, Corp.
FQV01 · FQV02 · FQV03 · FQV04 · FQV05
3.3 Volt Asynchronous x9 First-In/First-Out Queue
FlexQ
TM
Async
3.3 Volt Asynchronous x9 First-In/First-Out Queue
Memory
8,192 x 9
4,096 x 9
2,048 x 9
1,024 x 9
512 x 9
Device
FQV05
FQV04
FQV03
FQV02
FQV01
Key Features:
•
•
•
•
•
•
•
•
•
•
•
•
Industry leading First-In/First-Out Queues (up to 50MHz)
Independent Write and Read cycle time
Asynchronous and simultaneous read and write
3.3V power supply
Fully expandable in both word depth and width
Retransmit capability
Full, Empty, and Half Full flag indicators
Available packages: 32-pin Plastic Lead Chip Carrier (PLCC)
All Pb-free (Lead-free) products are RoHS compliant
°
°
(0 C to 70 C) Commercial operating temperature available for access time of 12ns and above
(-40
°
C to 85
°
C) Industrial operating temperature available for access time of 25ns
Pin-to-pin compatible with IDT (72V01, 72V02, 72V03, 72V04, 72V05)
Product Description:
AMIC’s FlexQ™ Async FIFO offers industry leading 0.25um process technology and memory densities from 512 x 9 to
8,192 x 9. System designer has full flexibility of implementing deeper and wider queues using the depth and width
expansion features. Full and Empty indicators allow easy handshaking between transmitters and receivers.
Independent Write and Read controls
________
provide rate-matching capability. System designer can re-read data from the
starting position by using Retransmit (RET). Retransmit allows reset of the read pointer to its initial position. Half Full flag
__________
(HALF) is available in the single device mode and width expansion mode, but not in depth expansion mode.
These FlexQ™ Async devices have low power consumption, hence minimizing system power requirements. In addition,
industry standard 32 - pin PLCC are offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, medical systems, network switching, etc.
(May, 2006, Version D)
1
AMIC Technology, Corp.
FQV01 · FQV02 · FQV03 · FQV04 · FQV05
FlexQ
TM
Async
READ (
R
)
FQV01
FQV02
FQV03
FQV04
FQV05
DATA OUT (Q
8 - 0
)
EMPTY (
EMPTY
)
RETRANSMIT ( RET )
EXPANSION OUT / HALF (
XO/
HALF
)
WRITE (
W
)
DATA IN (D
8 - 0
)
FULL (
FULL
)
RESET ( RST )
EXPANSION IN ( XI )
FIRST LOAD (
FIRST
)
Figure 1. Device Configuration Signal Flow Diagram
Block Diagram of Single Asynchronous Queue
8,192 x 9 / 4,096 x 9 / 2,048 x 9 / 1,024 x 9 / 512 x 9
W
Write Control
Logic
RST
RET
Reset Logic
Write Pointer
D
8-0
Input Register
SRAM
Output Register
Output
Buffer
Q
8-0
Read Pointer
FIRST
XI
EMPTY
Expansion
Logic
XO
Read Control
Logic
Flag
Logic
FULL
HALF
R
Figure 2. Device Architecture
(May, 2006, Version D)
1
AMIC Technology, Corp.
FQV01 · FQV02 · FQV03 · FQV04 · FQV05
FlexQ
TM
Async
Vcc
NC
D8
D4
31
D3
Index
4
3
W
2
1
32
D2
D1
D0
XI
FULL
Q0
Q1
NC
Q2
D5
30
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
14
D6
D7
NC
FIRST /
RET
RST
EMPTY
XO /
HALF
Q7
Q6
15
16
17
18
19
20
Q4
GND
Q3
Q8
PLCC - 32 (Drw No: J-01A; Order code: J)
Top View
Figure 3. Device Pin-Out
NC
Q5
R
(May, 2006, Version D)
2
AMIC Technology, Corp.
FQV01 · FQV02 · FQV03 · FQV04 · FQV05
FlexQ
TM
Async
Pin #
Symbol
Name
Input/
Output
Description
Reset is required to initialize Write and Read pointers to
the first position of the queue by setting
RST
low.
FULL
will go high;
EMPTY
will go low.
____
25
RST
Reset
Input
____
2
3, 4, 5, 6,
7, 28, 29,
30, 31
18
10, 11,
13, 14,
15, 19,
20 21
26
W
Write
Input
Writes data into queue during low to high transitions of
W if queue is not full yet.
D
8 - 0
___
Data Inputs
Input
9 - bit wide input data bus.
R
Read
Input
Reads data from queue during high to low transitions of
___
R if queue is not empty.
9 - bit wide output data bus.
___________
________
Q
8 - 0
Data Output
Output
___________
FIRST /
________
RET
First Load/
Retransmit
Input
FIRST / RET is used differently depending on mode. In
Depth Expansion Mode, the pin is grounded to indicate
first load. In Single Device Mode, the pin acts as
retransmit
____
____
8
XI
Expansion In
Input
XI is used to indicate operations in different modes.
When the pin is grounded, it indicates an operation in
the Single Device Mode. When it is tied to Vcc, it
indicates an operation in Depth Expansion Mode.
Queue is full when
FULL
goes low. This prohibits
further writes into the queue. The
____
assertion of
FULL
is
synchronous to the falling edge of W and the
___
deassertion is synchronous to the rising edge of R.
Queue is empty when
EMPTY
goes low. This prohibits
further reads from the queue. The assertion of
EMPTY
___
is synchronous to the falling edge of R and the
____
deassertion is synchronous to the rising edge of W.
______
__________
9
FULL
Full Flag
Output
24
EMPTY
Empty Flag
Output
______
23
XO /
HALF
__________
Expansion
Out / Half Full
Flag
Output
XO / HALF is used differently depending on mode. In
____
Depth Expansion Mode, XI is connected to the previous
______
device’s XO pin. When the previous device has reached
the last location of memory, this pin will send pulses to
the next device in the Daisy Chain. In Single Device
____
Mode, when XI is grounded, this pin indicates queue is
half-full.
3.3V power supply.
0V Ground.
No connection.
32
16
1, 12, 17,
27
Vcc
GND
NC
Power
Ground
No
Connection
N/A
N/A
N/A
Table 1. Pin Descriptions
(May, 2006, Version D)
3
AMIC Technology, Corp.
Microcontroller MCU
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