CY7C1360C
CY7C1362C
9-Mbit (256K × 36/512K × 18)
Pipelined SRAM
9-Mbit (256K × 36/512K × 18) Pipelined SRAM
Features
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Functional Description
The CY7C1360C/CY7C1362C SRAM integrates 256K × 36 and
512K × 18 SRAM cells with advanced synchronous peripheral
circuitry and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE
1
), depth-expansion chip enables (CE
2
and
CE
3[1]
), burst control inputs (ADSC, ADSP, and ADV), write
enables (BW
X
, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
Addresses and chip enables are registered at the rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see
Pin Definitions on page 8
and
Truth Table on
page 11
for further details). Write cycles can be one to two or four
bytes wide as controlled by the byte write control inputs. GW
when active LOW causes all bytes to be written.
The CY7C1360C/CY7C1362C operate from a +3.3 V core power
supply while all outputs may operate with either a +2.5 or +3.3 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click
here.
Supports bus operation up to 200 MHz
Available speed grades: 200 MHz, and 166 MHz
Registered inputs and outputs for pipelined operation
3.3 V core power supply (V
DD
)
2.5 V/3.3 V I/O operation (V
DDQ
)
Fast clock-to-output times
❐
3.0 ns (for 200 MHz device)
Provide high performance 3-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single cycle chip deselect
Available in Pb-free 100-pin TQFP package, non Pb-free
119-ball BGA package, and 165-ball FBGA package
TQFP available with 3-chip enable and 2-chip enable
IEEE 1149.1 JTAG-compatible boundary scan
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Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
200 MHz
3.0
220
40
166 MHz
3.5
180
40
Unit
ns
mA
mA
Note
1. CE
3
is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.
Cypress Semiconductor Corporation
Document Number: 38-05540 Rev. *S
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 11, 2018
CY7C1360C
CY7C1362C
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Single Write Accesses Initiated by ADSP ................... 9
Single Write Accesses Initiated by ADSC ................. 10
Burst Sequences ....................................................... 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Partial Truth Table for Read/Write ................................ 12
Partial Truth Table for Read/Write ................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 17
3.3 V TAP AC Test Conditions ....................................... 17
3.3 V TAP AC Output Load Equivalent ......................... 17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Boundary Scan Order .................................................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Neutron Soft Error Immunity ......................................... 22
Electrical Characteristics ............................................... 22
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 24
Switching Characteristics .............................................. 25
Switching Waveforms .................................................... 26
Ordering Information ...................................................... 30
Ordering Code Definitions ......................................... 30
Package Diagrams .......................................................... 31
Acronyms ........................................................................ 34
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
Document History Page ................................................. 35
Sales, Solutions, and Legal Information ...................... 38
Worldwide Sales and Design Support ....................... 38
Products .................................................................... 38
PSoC® Solutions ...................................................... 38
Cypress Developer Community ................................. 38
Technical Support ..................................................... 38
Document Number: 38-05540 Rev. *S
Page 3 of 38
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